Method and software for partitioned floating-point multiply-add operation

• US 20040205324A1
• Filed: 01/16/2004
• Published: 10/14/2004
• Est. Priority Date: 08/16/1995
• Status: Active Grant

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Granted Patent: US 7,660,972 B2
• Time in Patent Office: Days
• US Class Current: 712/222
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A method and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply the first and second registers and add the third register to produce a catenated result containing a plurality of data elements. Additional instructions provide group floating-point subtract, add, multiply, set less, and set greater equal operations. The set less and set greater equal operations produce alternatively zero or an identity element for each element of a catenated result, the result facilitating alternative selection of individual data elements using bitwise Boolean operations and without requiring conditional branch operations.

Claims

1. A method for processing data in a programmable processor, the method comprising:

decoding and executing instructions that instruct a computer system to perform operations,

at least some of the instructions including a group floating-point instruction operating on first and second registers partitioned into a plurality of floating point operands, the floating point operands having a defined precision and the defined precision being dynamically variable, having a defined result precision which is equal to the defined precision of the operands;

at least some group floating-point instruction being a group floating-point multiply-and-add instruction, further operating on a third register partitioned into a plurality of floating-point operands,

operable to multiply the plurality of floating-point operands in the first and second registers and add the plurality of floating-point operands in the third register, each producing a floating-point value to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for receiving the plurality of floating point values.

2. The method of claim 1,

at least some group floating-point instruction being at least one member of the collection consisting of group floating-point subtract, group floating-point add, and group floating-point multiply,

operable to perform a subtract, add and multiply respectively on the plurality of floating-point operands in the first and second registers, each producing a floating-point value to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for receiving the plurality of floating point values;

and

at least some group floating-point instruction being at least one member of the collection consisting of group floating-point set less, and group floating-point set greater or equal,

operable to perform a set-less and set-greater-or-equal operation, respectively, on the plurality of floating-point operands in the first and second registers, each producing a value to provide a plurality of values, each of the values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for receiving the plurality of values, wherein the value is zero if the operation produces a false result, and wherein the value is an identity value if the operation produces a true result; and

at least some of the instructions comprising performing data manipulations on multiple operands stored in partitioned fields of registers wherein the data manipulations comprise copying or rearranging operands.

3. The method of claim 2 wherein the zero value and the identity value are values that construct a bit mask operable to select between alternate expressions using a bitwise Boolean operation.

4. The method of claim 1 wherein the catenated result has a width of 128 bits.

5. The method of claim 1 wherein the catenated result is provided to a register.

6. The method of claim 1 wherein the defined precision is 16 bits.

7. The method of claim 1 wherein the defined precision is a format comprising one sign bit, five exponent bits and ten significand bits.

8. The method of claim 1 wherein the defined precision is 32 bits.

9. The method of claim 1 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eight exponent bits and 23 significand bits.

10. The method of claim 1 wherein the defined precision is 64 bits.

11. The method of claim 1 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eleven exponent bits and 52 significand bits.

12. A computer-readable medium:

having instructions that instruct a computer system to perform operations,

at least some of the instructions including a group floating-point instruction operating on first and second registers partitioned into a plurality of floating point operands, the floating point operands having a defined precision and the defined precision being dynamically variable, having a defined result precision which is equal to the defined precision of the operands;

at least some group floating-point instruction being a group floating-point multiply-and-add instruction, further operating on a third register partitioned into a plurality of floating-point operands,

operable to multiply the plurality of floating-point operands in the first and second registers and add the plurality of floating-point operands in the third register, each producing a floating-point value to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for receiving the plurality of floating point values.

13. The computer-readable medium of claim 12,

at least some group floating-point instruction being at least one member of the collection consisting of group floating-point subtract, group floating-point add, and group floating-point multiply,

operable to perform a subtract, add and multiply respectively on the plurality of floating-point operands in the first and second registers, each producing a floating-point value to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for receiving the plurality of floating point values;

and

at least some group floating-point instruction being at least one member of the collection consisting of group floating-point set less, and group floating-point set greater or equal,

operable to perform a set-less and set-greater-or-equal operation, respectively, on the plurality of floating-point operands in the first and second registers, each producing a value to provide a plurality of values, each of the values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for receiving the plurality of values, wherein the value is zero if the operation produces a false result, and wherein the value is an identity value if the operation produces a true result; and

at least some of the instructions comprising performing data manipulations on multiple operands stored in partitioned fields of registers wherein the data manipulations comprise copying or rearranging operands.

14. The computer-readable medium of claim 13 wherein the zero value and the identity value are values that construct a bit mask operable to select between alternate expressions using a bitwise Boolean operation.

15. The computer-readable medium of claim 12 wherein the catenated result has a width of 128 bits.

16. The computer-readable medium of claim 12 wherein the catenated result is provided to a register

17. The computer-readable medium of claim 12 wherein the defined precision is 16 bits.

18. The computer-readable medium of claim 12 wherein the defined precision is a format comprising one sign bit, five exponent bits and ten significand bits.

19. The computer-readable medium of claim 12 wherein the defined precision is 32 bits.

20. The computer-readable medium of claim 12 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eight exponent bits and 23 significand bits.

21. The computer-readable medium of claim 12 wherein the defined precision is 64 bits.

22. The computer-readable medium of claim 12 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eleven exponent bits and 52 significand bits.

23. A computer data signal, embodied in a transmission medium:

having instructions that instruct a computer system to perform operations,

at least some of the instructions including a group floating-point instruction operating on first and second registers partitioned into a plurality of floating point operands, the floating point operands having a defined precision and the defined precision being dynamically variable, having a defined result precision which is equal to the defined precision of the operands;

at least some group floating-point instruction being a group floating-point multiply-and-add instruction, further operating on a third register partitioned into a plurality of floating-point operands,

operable to multiply the plurality of floating-point operands in the first and second registers and add the plurality of floating-point operands in the third register, each producing a floating-point value to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for receiving the plurality of floating point values.

24. The computer data signal of claim 23,

at least some group floating-point instruction being at least one member of the collection consisting of group floating-point subtract, group floating-point add, and group floating-point multiply,

operable to perform a subtract, add and multiply respectively on the plurality of floating-point operands in the first and second registers, each producing a floating-point value to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for receiving the plurality of floating point values;

and

at least some group floating-point instruction being at least one member of the collection consisting of group floating-point set less, and group floating-point set greater or equal,

operable to perform a set-less and set-greater-or-equal operation, respectively, on the plurality of floating-point operands in the first and second registers, each producing a value to provide a plurality of values, each of the values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for receiving the plurality of values, wherein the value is zero if the operation produces a false result, and wherein the value is an identity value if the operation produces a true result; and

at least some of the instructions comprising performing data manipulations on multiple operands stored in partitioned fields of registers wherein the data manipulations comprise copying or rearranging operands.

25. The computer data signal of claim 24 wherein the zero value and the identity value are values that construct a bit mask operable to select between alternate expressions using a bitwise Boolean operation.

26. The computer data signal of claim 23 wherein the catenated result has a width of 128 bits.

27. The computer data signal of claim 23 wherein the defined precision is 16 bits.

28. The computer data signal of claim 23 wherein the defined precision is a format comprising one sign bit, five exponent bits and ten significand bits.

29. The computer data signal of claim 23 wherein the defined precision is 32 bits.

30. The computer data signal of claim 23 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eight exponent bits and 23 significand bits.

31. The computer data signal of claim 23 wherein the defined precision is 64 bits.

32. The computer data signal of claim 23 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eleven exponent bits and 52 significand bits.