Three-dimensional memory device with ECC circuitry

• US 20040206982A1
• Filed: 05/06/2004
• Published: 10/21/2004
• Est. Priority Date: 09/15/2000
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Lee, Thomas H., Johnson, Mark G.
• Granted Patent: US 7,203,084 B2
• Time in Patent Office: Days
• US Class Current: 257/200
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 2003/0697 device management, e.g. handlers, drivers, I/O schedulers
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/08 from or to individual record carriers, e.g. punched card , memory card, integrated circuit [IC] card or smart card
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: Y10S 707/99934 Query formulation, input preparation, or translation
• CPC Class Codes: Y10S 707/99943 Generating database or data structure, e.g. via user interface
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99956 File allocation

Abstract

The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition. Additionally, methods for permanently preventing modification of data stored in a memory device and for identifying memory cells storing data are disclosed.

Claims

1. A three-dimensional memory device with ECC circuitry comprising:

a support element;

error checking and correcting (ECC) circuitry carried by the support element; and

a memory array carried by the support element, wherein the memory array comprises;

a first conductor;

a first memory cell stacked vertically above the first conductor;

a second conductor stacked vertically above the first memory cell; and

a second memory cell stacked vertically above the second conductor;

wherein the second conductor is the only conductor between the first and second memory cells.

2. The invention of claim 1 further comprising a housing protecting the error checking and correcting (ECC) circuitry and the memory array.

3. The invention of claim 1, wherein the memory cells comprise write-once memory cells.

4. The invention of claim 1, wherein the memory cells are selected from the group consisting of semiconductor-transistor-technology-based memory cells, magnetic-based memory cells, and organic-electronics-based memory cells.

5. A method for storing data and error checking and correcting (ECC) bits in a three-dimensional memory device with ECC circuitry, the method comprising:

(a) providing a three-dimensional memory device with ECC circuitry to a data storage system, the memory device comprising;

a support element;

error checking and correcting (ECC) circuitry carried by the support element; and

a memory array carried by the support element, wherein the memory array comprises;

a first conductor;

a first memory cell stacked vertically above the first conductor;

a second conductor stacked vertically above the first memory cell; and

a second memory cell stacked vertically above the second conductor;

wherein the second conductor is the only conductor between the first and second memory cells;

(b) with the memory device, receiving at least one data bit to be stored in the memory array;

(c) with the ECC circuitry, generating at least one ECC bit based on the at least one data bit; and

(d) storing the at least one data bit and the at least one ECC bit in the memory array.

6. The invention of claim 5 further comprising:

(e) retrieving the at least one data bit and the at least one ECC bit in the memory array; and

(f) with the ECC circuitry, identifying an error in the retrieved at least one data bit and at least one ECC bit.

7. The invention of claim 5, wherein the memory device further comprises a housing protecting the error checking and correcting (ECC) circuitry and the memory array.

8. The invention of claim 5, wherein the memory cells comprise write-once memory cells.

9. The invention of claim 5, wherein the memory cells are selected from the group consisting of semiconductor-transistor-technology-based memory cells, magnetic-based memory cells, and organic-electronics-based memory cells.