Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate

• US 20040207006A1
• Filed: 05/17/2004
• Published: 10/21/2004
• Est. Priority Date: 09/19/2002
• Status: Active Grant

• Current Assignee: Vei-Han Chan, Yi Ding
• Original Assignee: Vei-Han Chan, Yi Ding
• Inventors: Chan, Vei-Han, Ding, Yi
• Granted Patent: US 7,057,231 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell'"'"'s floating gate transistor has a first source/drain region (226), a channel region (224), and a second source/drain region (130). The dielectric (128) is stronger against leakage near at least a portion of the first source/drain region (122) than near at least a portion of the channel region. The stronger portion (128.1) of the additional dielectric improves data retention without increasing the programming and erase times if the programming and erase operations do not rely on a current through the stronger portion. Additional dielectric (210) has a portion located below the top surface of the substrate between the trench and a top part of the second source/drain region (130). The second source/drain region has a part located below the additional dielectric and meeting the trench. The additional dielectric can be formed with shallow trench isolation technology. The additional dielectric reduces the capacitance between the second source/drain region (130) and the floating gate.

Claims

1. An integrated circuit comprising a first nonvolatile memory cell, the integrated circuit comprising:

a semiconductor substrate having a top surface and a trench formed in the top surface;

a dielectric on a surface of the trench;

a conductive floating gate at least partially located in the trench;

wherein the first nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate, and comprises a second FET for controlling access to the first FET;

wherein the substrate comprises;

a first semiconductor region of a first conductivity type adjacent to the trench and providing a first source/drain region for the first FET;

a second semiconductor region of a second conductivity type adjacent to the trench above the first semiconductor region and providing a channel region for the first FET;

a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the trench above the second semiconductor region and provides a second source/drain region for the first FET, wherein the third semiconductor region also provides a source/drain region for the second FET;

a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and

a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET;

wherein the integrated circuit further comprises a conductive member having a portion overlying the trench, wherein the conductive member provides a gate for the second FET.

2. The integrated circuit of claim 1 wherein said portion of the conductive member overlies the floating gate.

3. The integrated circuit of claim 1 wherein the third semiconductor region curves around the trench adjacent to the trench.

4. The integrated circuit of claim 1 wherein the first and second source/drain regions of the first FET and the channel region of the first FET curve around the trench.

5. The integrated circuit of claim 4 wherein the first and second semiconductor regions laterally surround the trench.

6. The integrated circuit of claim 1 wherein the entire third semiconductor region is located on one side of the trench.

7. The integrated circuit of claim 5 wherein the third, fourth and fifth semiconductor regions are entirely located on one side of the trench.

8. The integrated circuit of claim 1 further comprising a dielectric region having at least a portion extending below the top surface of the substrate between the trench and a top part of the third semiconductor region, wherein the third semiconductor region has a part located below said portion of the dielectric region and meeting the trench.

9. The integrated circuit of claim 8 wherein the dielectric region has a portion extending below the top surface of the substrate and overlapping the trench.

10. The integrated circuit of claim 1 wherein the dielectric on the surface of the trench is stronger against leakage adjacent at least a portion of the first semiconductor region than adjacent at least a portion of the second semiconductor region.

11. The integrated circuit of claim 10 wherein a stronger portion of the dielectric adjacent the first semiconductor region comprises silicon nitride, and a less strong portion of the dielectric adjacent the second semiconductor region consists of silicon oxide.

12. The integrated circuit of claim 1 wherein all of the floating gate is in the trench.

13. The integrated circuit of claim 12 wherein the floating gate is below the top surface of the semiconductor substrate.

14. The integrated circuit of claim 1 comprising a plurality of nonvolatile memory cells, the first nonvolatile memory cell being one of the plurality;

wherein the semiconductor substrate comprises, for each cell, a trench formed in the top surface of the substrate;

wherein the integrated circuit comprises, for each cell, a dielectric on the surface of the respective trench and a floating gate at least partially located in the respective trench;

wherein each cell comprises a respective first FET whose conductivity is at least partially controlled by the respective floating gate, and comprises a respective second FET for controlling access to the respective first FET;

wherein the substrate comprises, for each cell;

a first semiconductor region of a first conductivity type adjacent to the respective trench and providing a first source/drain region for the first FET of the cell;

a second semiconductor region of a second conductivity type adjacent to the respective trench above the respective first semiconductor region and providing a channel region for the first FET of the cell;

a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the respective trench above the respective second semiconductor region and provides a second source/drain region for the first FET of the cell, wherein the third semiconductor region also provides a source/drain region for the second FET of the cell;

a fourth semiconductor region of the second conductivity type adjacent to the respective third semiconductor region and providing a channel region for the second FET of the cell; and

a fifth semiconductor region of the first conductivity type adjacent to the respective fourth semiconductor region and providing a source/drain region for the second FET of the cell;

wherein the integrated circuit further comprises a plurality of wordlines, each wordline being for selecting a subset of the memory cells, wherein each wordline has portions overlying the trenches of the corresponding subset of the memory cells and provides gates for the second FETs of the corresponding subset of the memory cells, said conductive member being one of the wordlines.

15. The integrated circuit of claim 14 wherein said portions of each wordline overlie the floating gates of the corresponding subset of the memory cells.

16. The integrated circuit of claim 14 wherein the plurality of wordlines comprises a plurality of pairs of adjacent wordlines, wherein for each pair of wordlines, a memory cell corresponding to one of the wordlines and a memory cell corresponding to the other one of the wordlines have their fifth semiconductor regions merged together.

17. The integrated circuit of claim 14 wherein the memory cells form an array of rows and columns, each wordline being for selecting one row, wherein the rows are a plurality of pairs of adjacent rows, and in each pair of rows, the memory cells in each column have their, fifth semiconductor regions merged together.

18. The integrated circuit of claim 17 wherein in each column of the memory cells, all of the third, fourth and fifth semiconductor regions are entirely located on one side of an area occupied by the trenches.

19. A method for fabricating the integrated circuit of claim 1, the method comprising:

forming the trench in the top surface of the semiconductor substrate;

forming the dielectric on the surface of the trench;

forming the conductive floating gate at least partially located in the trench; and

forming the conductive member.

20. An integrated circuit comprising a nonvolatile memory cell, the integrated circuit comprising:

a semiconductor substrate having a top surface and a first trench formed in the top surface;

a dielectric on a surface of the first trench;

a conductive floating gate at least partially located in the first trench;

wherein the nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate;

wherein the substrate comprises;

a first semiconductor region of a first conductivity type adjacent to the first trench and providing a first source/drain region for the first FET;

a second semiconductor region of a second conductivity type adjacent to the first trench above the first semiconductor region and providing a channel region for the first FET;

a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the first trench above the second semiconductor region and provides a second source/drain region for the first FET;

wherein the integrated circuit further comprises a dielectric region having at least a portion extending below the top surface of the substrate between the first trench and a top part of the third semiconductor region, wherein the third semiconductor region has a part located below said portion of the dielectric region and meeting the first trench.

21. The integrated circuit of claim 20 wherein the dielectric region has a portion extending below the top surface of the substrate and overlapping the first trench.

22. The integrated circuit of claim 20 wherein the nonvolatile memory cell comprises a second FET for controlling access to the first FET;

wherein the third semiconductor region provides a source/drain region for the second FET;

wherein the substrate comprises;

a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and

a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET;

wherein the integrated circuit further comprises a conductive gate for the second FET.

23. The integrated circuit of claim 20 wherein the dielectric on the surface of the first trench is stronger against leakage adjacent at least a portion of the first semiconductor region than adjacent at least a portion of the second semiconductor region.

24. The integrated circuit of claim 23 wherein a stronger portion of the dielectric adjacent at least the portion of the first semiconductor region comprises silicon nitride, and a less strong portion of the dielectric adjacent at least the portion of the second semiconductor region consists of silicon oxide.

25. The integrated circuit of claim 20 wherein all of the floating gate is in the first trench.

26. The integrated circuit of claim 25 wherein the floating gate is below the top surface of the semiconductor substrate.

27. A method for fabricating the integrated circuit of claim 20, the method comprising:

forming the first trench in the top surface of the semiconductor substrate;

forming the dielectric on the surface of the first trench;

forming the floating gate at least partially located in the first trench; and

forming the dielectric region.

28. The method of claim 27 wherein, in the integrated circuit:

the nonvolatile memory cell comprises a second FET for controlling access to the first FET;

the third semiconductor region provides a source/drain region for the second FET;

the substrate comprises;

a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and

a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET;

wherein the method further comprises forming a conductive gate for the second FET.

29. The method of claim 27 comprising forming a field dielectric layer to isolate active areas of the integrated circuit, wherein the dielectric region is part of the field dielectric layer.

30. The method of claim 27 wherein forming at least said portion of the dielectric region comprises:

forming a second trench in the top surface of the substrate; and

filling the second trench with dielectric.

31. The method of claim 30 wherein the second trench is not as deep as the first trench.

32. The method of claim 30 further comprising, after forming the second trench but before filling the second trench with the dielectric, introducing a dopant into a bottom surface of the second trench adjacent to the first trench to dope at least a portion of the third semiconductor region.

33. An integrated circuit comprising:

a semiconductor substrate having a top surface and a trench formed in the top surface;

a first dielectric on a surface of the trench;

a conductive floating gate at least partially located in the trench;

wherein the nonvolatile memory cell comprises a first field effect transistor (FET) comprising said floating gate;

wherein the substrate comprises;

a first semiconductor region of a first conductivity type adjacent to the trench and providing a first source/drain region for the first FET;

a second semiconductor region of a second conductivity type adjacent to the trench above the first semiconductor region and providing a channel region for the first FET;

a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the trench above the second semiconductor region and provides a second source/drain region for the first FET;

wherein the first dielectric comprises a first portion and a second portion, the first portion being stronger against leakage than the second portion, wherein at least part of the first semiconductor region is adjacent to the first portion of the first dielectric, and at least part of the second semiconductor region is adjacent to the second portion of the first dielectric.

34. The integrated circuit of claim 33 wherein the first portion of the first dielectric comprises silicon nitride, and the second portion of the first dielectric consists of silicon oxide.

35. The integrated circuit of claim 33 wherein all of the first portion of the first dielectric is adjacent to the first semiconductor region.

36. The integrated circuit of claim 33 wherein some of the second portion of the first dielectric is adjacent to the first semiconductor region.

37. The integrated circuit of claim 33 wherein the second portion of the first dielectric is located above the first portion of the first dielectric.

38. The integrated circuit of claim 37 wherein the first semiconductor region extends up higher than the first portion of the first dielectric and meets the second portion of the first dielectric.

39. The integrated circuit of claim 33 wherein the memory cell further comprises a second FET for controlling access to the first FET;

wherein the third semiconductor region also provides a source/drain region for the second FET;

wherein the substrate further comprises;

a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and

a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET;

wherein the integrated circuit further comprises a conductive gate for the second FET.

40. A method for fabricating the integrated circuit of claim 33, the method comprising:

forming the trench in the top surface of the semiconductor substrate;

forming the first and second portions of the first dielectric on the surface of the trench; and

forming the floating gate at least partially located in the trench.

41. The method of claim 40 wherein the first portion of the first dielectric comprises silicon nitride, and the second portion of the first dielectric consists of silicon oxide.

42. The method of claim 40 wherein all of the first portion of the first dielectric is adjacent to the first semiconductor region.

43. The method of claim 40 wherein some of the second portion of the first dielectric is adjacent to the first semiconductor region.

44. The method of claim 40 wherein the second portion of the first dielectric is located above the first portion of the first dielectric.

45. The method of claim 44 wherein the first semiconductor region extends up higher than the first portion of the first dielectric and meets the second portion of the first dielectric.

46. The method of claim 40 wherein, in the integrated circuit:

the memory cell further comprises a second FET for controlling access to the first FET;

wherein the third semiconductor region also provides a source/drain region for the second FET;

wherein the substrate further comprises;

a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and

a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET;

wherein the method further comprises forming a conductive gate for the second FET.