TEST STRUCTURE AND RELATED METHODS FOR EVALUATING STRESS-INDUCED VOIDING

• US 20040207383A1
• Filed: 04/21/2003
• Published: 10/21/2004
• Est. Priority Date: 04/21/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chien-Jung
• Granted Patent: US 6,897,475 B2
• Time in Patent Office: Days
• US Class Current: 324/71.2
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

This disclosure provides, in one aspect, a test structure formed within a semiconductor wafer. In one embodiment, the test structure comprises a plurality of first level bulk metals having varying sizes, where adjacent ones of the plurality of first level bulk metals are coupled together using vias connected to second level thin conductors located therebetween. In addition, the test structure comprises a plurality of second level bulk metals having varying sizes, where adjacent ones of the plurality of second level bulk metals are coupled together using vias connected to first level thin conductors located therebetween. Furthermore, the test structure includes a first level contact pad coupled to a smallest of the plurality of second level bulk metals, and a second level contact pad coupled to a largest of the plurality of first level bulk metals. In such an embodiment, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals. In other aspects, this disclosure provides a method of manufacturing a test structure within a semiconductor wafer, and a method of evaluating stress-induced voiding of metals within a semiconductor wafer.

Claims

1. A test structure formed within a semiconductor wafer, comprising:

a plurality of first level bulk metals having varying sizes, adjacent ones of the plurality of first level bulk metals coupled together using vias connected to second level thin conductors located therebetween;

a plurality of second level bulk metals having varying sizes, adjacent ones of the plurality of second level bulk metals coupled together using vias connected to first level thin conductors located therebetween;

a first level contact pad coupled to a smallest of the plurality of second level bulk metals; and

a second level contact pad coupled to a largest of the plurality of first level bulk metals, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals.

2. The test structure as recited in claim 1, wherein the plurality of first level bulk metals having varying sizes comprises a plurality of first level bulk metals having varying lengths and widths, and wherein the plurality of second level bulk metals having varying sizes comprises a plurality of second level bulk metals having varying lengths and widths.

3. The test structure as recited in claim 1, wherein the plurality of first level bulk metals having varying sizes are arranged in ascending size, and the plurality of second level bulk metals having varying sizes are arranged in descending size.

4. The test structure as recited in claim 1, wherein the first and second level bulk metals each comprise first and second portions coupled together using a metal trace.

5. The test structure as recited in claim 1, wherein the first level bulk metals are located on a level over a level of the second level bulk metals.

6. The test structure as recited in claim 1, wherein a smallest of the second level bulk metals is located proximate a largest of the first level bulk metals, and wherein a largest of the second level bulk metals is located proximate a smallest of the first level bulk metals and coupled thereto using a via.

7. The test structure as recited in claim 1, wherein the first level contact pad is coupled to a smallest of the plurality of second level bulk metals using a via, and the second level contact pad is coupled to a largest of the plurality of first level bulk metals using a via.

8. A method of manufacturing a test structure within a semiconductor wafer, comprising:

forming a plurality of first level bulk metals having varying sizes and a plurality of second level bulk metals having varying sizes on the wafer;

coupling adjacent ones of the plurality of first level bulk metals together using vias connected to second level thin conductors located therebetween;

coupling adjacent ones of the plurality of second level bulk metals together using vias connected to first level thin conductors located therebetween;

coupling a first level contact pad to a smallest of the plurality of second level bulk metals;

coupling a second level contact pad to a largest of the plurality of first level bulk metals; and

coupling a largest of the second level bulk metals to a smallest of the first level bulk metals.

9. The method as recited in claim 8, wherein forming a plurality of first level bulk metals and a plurality of second level bulk metals on the wafer comprises forming a plurality of first level bulk metals having lengths and widths, and forming a plurality of second level bulk metals having varying lengths and widths.

10. The method as recited in claim 8, wherein forming a plurality of first level bulk metals and a plurality of second level bulk metals on the wafer comprises forming a plurality of first level bulk metals arranged in ascending size, and forming a plurality of second level bulk metals arranged in descending size.

11. The method as recited in claim 8, wherein the first and second level bulk metals each comprise first and second portions coupled together using a metal trace.

12. The method as recited in claim 8, wherein forming a plurality of first level bulk metals and a plurality of second level bulk metals on the wafer comprises forming the first level bulk metals on a level over a level of the second level bulk metals.

13. The method as recited in claim 8, further comprising locating a smallest of the second level bulk metals proximate a largest of the first level bulk metals, locating a largest of the second level bulk metals proximate a smallest of the first level bulk metals, and coupling the largest of the second level bulk metals to the smallest of the first level bulk metals using a via.

14. The method as recited in claim 8, further comprising coupling the first level contact pad to a smallest of the plurality of second level bulk metals using a via, and coupling the second level contact pad to a largest of the plurality of first level bulk metals using a via.

15. A method of evaluating stress-induced voiding of metals within a semiconductor wafer, comprising:

contacting a first probe to a first level contact pad coupled to a smallest of a plurality of second level bulk metals having varying sizes, adjacent ones of the plurality of second level bulk metals coupled together using vias connected to first level thin conductors located therebetween;

contacting a second probe to a second level contact pad coupled to a largest of a plurality of first level bulk metals having varying sizes, adjacent ones of the plurality of first level bulk metals coupled together using vias connected to second level thin conductors located therebetween, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals; and

determining a resistance across the pluralities of first and second level bulk metals using the first and second probes.

16. The method as recited in claim 15, further comprising contacting a first probe to a first level contact pad coupled to a smallest of a plurality of second level bulk metals having varying lengths and widths, and contacting a second probe to a second level contact pad coupled to a largest of a plurality of first level bulk metals having varying lengths and widths.

17. The method as recited in claim 15, wherein the plurality of first level bulk metals having varying sizes are arranged in ascending size, and the plurality of second level bulk metals having varying sizes are arranged in descending size.

18. The method as recited in claim 15, wherein the first and second level bulk metals each comprise first and second portions coupled together using a metal trace.

19. The method as recited in claim 15, wherein a smallest of the second level bulk metals is located proximate a largest of the first level bulk metals, and wherein a largest of the second level bulk metals is located proximate a smallest of the first level bulk metals and coupled thereto using a via.

20. The method as recited in claim 15, wherein the first level contact pad is coupled to a smallest of the plurality of second level bulk metals using a via, and the second level contact pad is coupled to a largest of the plurality of first level bulk metals using a via.