TEST STRUCTURE AND RELATED METHODS FOR EVALUATING STRESS-INDUCED VOIDING
First Claim
1. A test structure formed within a semiconductor wafer, comprising:
- a plurality of first level bulk metals having varying sizes, adjacent ones of the plurality of first level bulk metals coupled together using vias connected to second level thin conductors located therebetween;
a plurality of second level bulk metals having varying sizes, adjacent ones of the plurality of second level bulk metals coupled together using vias connected to first level thin conductors located therebetween;
a first level contact pad coupled to a smallest of the plurality of second level bulk metals; and
a second level contact pad coupled to a largest of the plurality of first level bulk metals, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals.
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Abstract
This disclosure provides, in one aspect, a test structure formed within a semiconductor wafer. In one embodiment, the test structure comprises a plurality of first level bulk metals having varying sizes, where adjacent ones of the plurality of first level bulk metals are coupled together using vias connected to second level thin conductors located therebetween. In addition, the test structure comprises a plurality of second level bulk metals having varying sizes, where adjacent ones of the plurality of second level bulk metals are coupled together using vias connected to first level thin conductors located therebetween. Furthermore, the test structure includes a first level contact pad coupled to a smallest of the plurality of second level bulk metals, and a second level contact pad coupled to a largest of the plurality of first level bulk metals. In such an embodiment, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals. In other aspects, this disclosure provides a method of manufacturing a test structure within a semiconductor wafer, and a method of evaluating stress-induced voiding of metals within a semiconductor wafer.
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Citations
20 Claims
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1. A test structure formed within a semiconductor wafer, comprising:
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a plurality of first level bulk metals having varying sizes, adjacent ones of the plurality of first level bulk metals coupled together using vias connected to second level thin conductors located therebetween;
a plurality of second level bulk metals having varying sizes, adjacent ones of the plurality of second level bulk metals coupled together using vias connected to first level thin conductors located therebetween;
a first level contact pad coupled to a smallest of the plurality of second level bulk metals; and
a second level contact pad coupled to a largest of the plurality of first level bulk metals, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of manufacturing a test structure within a semiconductor wafer, comprising:
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forming a plurality of first level bulk metals having varying sizes and a plurality of second level bulk metals having varying sizes on the wafer;
coupling adjacent ones of the plurality of first level bulk metals together using vias connected to second level thin conductors located therebetween;
coupling adjacent ones of the plurality of second level bulk metals together using vias connected to first level thin conductors located therebetween;
coupling a first level contact pad to a smallest of the plurality of second level bulk metals;
coupling a second level contact pad to a largest of the plurality of first level bulk metals; and
coupling a largest of the second level bulk metals to a smallest of the first level bulk metals. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method of evaluating stress-induced voiding of metals within a semiconductor wafer, comprising:
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contacting a first probe to a first level contact pad coupled to a smallest of a plurality of second level bulk metals having varying sizes, adjacent ones of the plurality of second level bulk metals coupled together using vias connected to first level thin conductors located therebetween;
contacting a second probe to a second level contact pad coupled to a largest of a plurality of first level bulk metals having varying sizes, adjacent ones of the plurality of first level bulk metals coupled together using vias connected to second level thin conductors located therebetween, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals; and
determining a resistance across the pluralities of first and second level bulk metals using the first and second probes. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification