High throughput reconfigurable data analysis system
First Claim
1. A reconfigurable detector comprising:
- at least one array of a plurality of pixels, each of the plurality of pixels selected to receive and read-out an input;
wherein the pixel array is divided into at least one pixel group for conducting a common predefined analysis, wherein each of the pixel groups is comprised of at least two pixels;
each of the plurality of pixels having a programmable circuitry, in communication therewith, each of said circuitry being programmed with a dynamically configurable user-defined function such that each of said circuitry receives the input from the selected pixel and outputs a modified input; and
a summing circuit in communication with the plurality of programmable circuits, said summing circuit designed to sum the modified inputs from the common pixel group in a single binning instruction to generate a scalar output for the pixel group.
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Abstract
The present invention relates to a system and method for performing rapid and programmable analysis of data. The present invention relates to a reconfigurable detector comprising at least one array of a plurality of pixels, where each of the plurality of pixels can be selected to receive and read-out an input. The pixel array is divided into at least one pixel group for conducting a common predefined analysis. Each of the pixels has a programmable circuitry programmed with a dynamically configurable user-defined function to modify the input. The present detector also comprises a summing circuit designed to sum the modified input.
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Citations
52 Claims
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1. A reconfigurable detector comprising:
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at least one array of a plurality of pixels, each of the plurality of pixels selected to receive and read-out an input;
wherein the pixel array is divided into at least one pixel group for conducting a common predefined analysis, wherein each of the pixel groups is comprised of at least two pixels;
each of the plurality of pixels having a programmable circuitry, in communication therewith, each of said circuitry being programmed with a dynamically configurable user-defined function such that each of said circuitry receives the input from the selected pixel and outputs a modified input; and
a summing circuit in communication with the plurality of programmable circuits, said summing circuit designed to sum the modified inputs from the common pixel group in a single binning instruction to generate a scalar output for the pixel group. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A reconfigurable detector for simultaneously detecting a plurality of targets, the detector comprising:
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at least one array of a plurality of pixels, each of the plurality of pixels selected to receive and read-out an input;
wherein the pixel array is divided into at least one pixel group for conducting a common predefined analysis, wherein each of the pixel groups is comprised of at least two pixels;
each of the plurality of pixels having at least two programmable circuitries designed to simultaneously perform calculations to detect the plurality of targets, in communication therewith, each of said circuitries being programmed with a dynamically configurable user-defined function associated with a target species such that each of said circuitries receives the input from the selected pixel and outputs a modified input; and
at least two summing circuits associated with the plurality of programmable circuitries and designed to simultaneously generate outputs representative of the plurality of targets, each of said summing circuits designed to sum the modified inputs from the associated one of the programmable circuitries to simultaneously generate a scalar output representative of the desired target. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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Specification