ELECTRONIC PARTS PACKAGING STRUCTURE AND METHOD OF MANUFACTURING THE SAME

• US 20040209399A1
• Filed: 06/02/2004
• Published: 10/21/2004
• Est. Priority Date: 12/03/2002
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: MASHINO, Naohiro, MURAYAMA, Kei, SUNOHARA, Masahiro, HIGASHI, Mitsutoshi
• Granted Patent: US 7,084,009 B2
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92124 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92224 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

There are included a wiring substrate including a predetermined wiring pattern, an electronic parts connection terminal on an element forming surface of which is flip-chip connected to the wiring pattern, an insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the electronic parts and the insulating film on the connection terminal, and an overlying wiring pattern formed on the insulating film and connected to the connection terminal via the via hole.

Claims

1. A method of manufacturing an electronic parts packaging structure, comprising the steps of:

flip-chip connecting a connection terminal of an electronic parts having the connection terminal on an element forming surface to a wiring pattern formed on or over a base substrate;

forming an insulating film for covering the electronic parts;

forming a via hole having a depth that reaches the connection terminal by etching a predetermined portion from an upper surface of the insulating film to the element forming surface of the electronic parts; and

forming an overlying wiring pattern, which is connected to the connection terminal via the via hole, on the insulating film.

3. A method of manufacturing an electronic parts packaging structure, according to claim 1, wherein, in the step of forming the via hole, the insulating film and the electronic parts are etched by RIE or a laser.

4. A method of manufacturing an electronic parts packaging structure, according to claim 1, wherein the step of forming the overlying wiring pattern includes the steps of,

forming a resist film having an opening portion in a predetermined portion containing the via hole on the insulating film,

forming a conductive film pattern in the via hole and the opening portion of the resist film, by applying a plating upward from the connection terminal exposed from a bottom portion of the via hole by means of electroplating that utilizes the wiring pattern and the connection terminal of the electronic parts connected to the wiring pattern as a plating power-supply layer, and removing the resist film to get the overlying wiring pattern.

5. A method of manufacturing an electronic parts packaging structure, according to claim 1, after the step of forming the via hole but before the step of forming the overlying wiring pattern, further comprising the steps of:

forming an inorganic insulating film on an inner surface of the via hole and on the insulating film; and

removing the inorganic insulating film from a bottom portion of the via hole to expose the connection terminal on the bottom portion of the via hole.

6. A method of manufacturing an electronic parts packaging structure, according to claim 1, wherein a structure in which a plurality of electronic parts are stacked three-dimensionally in a multi-layered fashion and are connected mutually via the via hole is formed by repeating n times (n is an integer of 1 or more) respective steps from the step of flip-chip connecting the electronic parts to the wiring pattern to the step of forming the overlying wiring pattern.

7. A method of manufacturing an electronic parts packaging structure, according to claim 1, after the step of forming the overlying wiring pattern, further comprising the step of:

flip-chip connecting a connection terminal of an overlying electronic parts having the connection terminal to the overlying wiring pattern.

8. A method of manufacturing an electronic parts packaging structure, according to claim 1, wherein the electronic parts is a semiconductor chip whose thickness is about 150 μ

m or less.

2. A method of manufacturing an electronic parts packaging structure, comprising the steps of:

flip-chip connecting a connection terminal of an electronic parts, which has the connection terminal on an element forming surface and has a through electrode connected to the connection terminal via a first via hole on a back surface, to a wiring pattern formed on or over a wiring substrate;

forming an insulating film for covering the electronic parts;

forming a second via hole having a depth that reaches the through electrode, by etching a predetermined portion of the insulating film on the through electrode; and

forming an overlying wiring pattern, which is connected to the through electrode via the second via hole, on the insulating film.