Controller with interface attachment

• US 20040209531A1
• Filed: 01/06/2004
• Published: 10/21/2004
• Est. Priority Date: 07/12/1999
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Charles M. Duppong
• Inventors: Duppong, Charles M.
• Granted Patent: US 6,925,407 B2
• Time in Patent Office: Days
• US Class Current: 439/894
• CPC Class Codes: G05B 2219/23417 Read program from pluggable memory card
• CPC Class Codes: G05B 2219/25265 Flash memory
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

A controller with attachments for controlling specific electronic circuits is disclosed. Each attachment has a connector connectable to the electronic circuit to be controlled, and a memory accessible by the controller that contains configuration data for accessing the electronic circuit, and operational software for operating the electronic circuit.

Claims

1-124. -124 (canceled)

125. A test system for testing an electronic circuit, said test system comprising:

a controller for testing the electronic circuit, said controller having a first connector; and

an application attachment having a second connector connectable to said first connector and a third connector connectable to the electronic circuit, said application attachment including a memory storing configuration data and a test program, said controller using the test program stored in said memory to test the electronic circuit.

126. The test system of claim 125, wherein the controller comprises a central processing unit and a programmable logic device, the central processing unit reading the configuration data and causing the programmable logic device to route signals between the controller and the electronic circuit.

127. The test system of claim 125, wherein the electronic circuit is an integrated circuit memory device.

128. The test system of claim 127, wherein the test program is a memory erase time test program.

129. The test system of claim 127, wherein the test program tests for failed memory locations in the integrated circuit memory device.

130. The test system of claim 125, wherein the electronic circuit is a memory circuit.

131. The test system of claim 130, wherein the test program is a memory erase time test program.

132. The test system of claim 130, wherein the test program tests for failed memory locations in the memory circuit.

133. The test system of claim 125, wherein said memory is a non-volatile memory device.

134. The test system of claim 125, wherein said memory is a flash memory device.

135. The test system of claim 125, wherein said application attachment further comprises a logic circuit connected between said second and third connectors.

136. A test system for testing an integrated circuit, said test system comprising:

a controller for testing the integrated circuit, said controller having a first connector; and

an application attachment having a second connector connectable to said first connector and an integrated circuit socket connectable to the integrated circuit, said application attachment including a memory storing configuration data and a test program, said controller using the test program stored in said memory to test the integrated circuit.

137. The test system of claim 136, wherein the controller comprises a central processing unit and a programmable logic device, the central processing unit reading the configuration data and causing the programmable logic device to route signals between the controller and the integrated circuit.

138. The test system of claim 136, wherein the integrated circuit is an integrated circuit memory device.

139. The test system of claim 138, wherein the test program is a memory erase time test program.

140. The test system of claim 138, wherein the test program tests for failed memory locations in the integrated circuit memory device.

141. The test system of claim 136, wherein said memory is a non-volatile memory device.

142. The test system of claim 136, wherein said memory is a flash memory device.

143. The test system of claim 136, wherein said application attachment further comprises a test circuit connected between said second connector and said integrated circuit socket.

144. A system for programming a memory device, said system comprising:

a controller for programming the memory device; and

an application attachment connectable between said controller and the memory device, said application attachment including a non-volatile memory storing configuration data and an operational program, said controller using the operational program stored in said non-volatile memory to program the memory device.

145. The system of claim 144, wherein said application attachment further comprises:

a first connector connectable to said controller;

a second connector connectable to the memory device; and

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a logic circuit connected between said first connector and said second connector.

146. A system for programming an integrated circuit memory device, said system comprising:

a controller for programming the integrated circuit memory device, said controller having a first connector; and

an application attachment having a second connector connectable to the first connector and an integrated circuit socket connectable to the integrated circuit memory device, said application attachment including a non-volatile memory storing configuration data and an operational program, said controller using the operational program stored in said non-volatile memory to program the integrated circuit memory device.

147. The system of claim 146, wherein said application attachment further comprises a test circuit connected between said second connector and said integrated circuit socket.

148. A system for debugging an electronic circuit, said system comprising:

a controller for debugging the electronic circuit; and

an application attachment connectable between said controller and the electronic circuit, said application attachment including a memory device storing configuration data and a debugging program, said controller using the debugging program to debug the electronic circuit.

149. A system for debugging an integrated circuit memory device, said system comprising:

a controller for debugging the integrated circuit memory device, said controller having a first connector; and

an application attachment having a second connector connectable to the first connector and an integrated circuit socket connectable to the integrated circuit memory device, said application attachment including a non-volatile memory storing configuration data and a debugging program, said controller using the program to debug the integrated circuit memory device.