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Network for decreasing transmit link layer core speed

  • US 20040210687A1
  • Filed: 03/23/2001
  • Published: 10/21/2004
  • Est. Priority Date: 03/23/2001
  • Status: Active Grant
First Claim
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1. A core for providing communications between a transmission media and a processor in a parallel-serial architecture, said core comprising:

  • serial lanes connecting said processor to said transmission media; and

    at least one selector connected to said serial lanes, whereby said selector selectively engages said serial lanes to alter a speed of data passing through said core.

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