Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms

• US 20040210719A1
• Filed: 05/10/2004
• Published: 10/21/2004
• Est. Priority Date: 11/19/2001
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Kelly Larson, Robert D. Bushey
• Inventors: Bushey, Robert D., Larson, Kelly
• Granted Patent: US 6,883,071 B2
• Time in Patent Office: Days
• US Class Current: 711/119
• CPC Class Codes: G06F 12/0817 using directory methods

Abstract

A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.

Claims

1. A system for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms, the system comprising:

a scalable symmetric multiple processor computer system, wherein the scalable symmetric multiple processor computer system comprises;

a central electronics complex (CEC),

one or more first buses connected to the CEC,

one or more first processor slots connected to the one or more first buses, and a memory;

an application specific integrated circuit (ASIC) replacing a processor in each of the one or more first processor slots of the scalable symmetric multiple processor computer system;

a first memory cache unit associated with each ASIC;

one or more second buses connected to each ASIC;

one or more second processors connected to each second bus; and

a second memory cache unit associated with each second processor.

2. The system of claim 1, wherein the memory, the first memory cache unit, and the second memory cache unit each comprise one or more multiple-byte cache lines.

3. The system of claim 2, wherein one byte of each the multiple-byte cache lines is reserved for access by one of the one or more second processors.

4. The system of claim 3, wherein the multiple-byte cache lines comprise 32 bytes.

5. The system of claim 3, wherein the multiple-byte cache lines comprise 64 bytes.

6. The system of claim 3 further comprising:

a memory address list that tracks memory addresses accessed by all memory read and write transactions; and

a transaction list that tracks status and data of all memory read and write transactions.

7. The system of claim 3, wherein the first buses comprise 64-bit buses.

8. The system of claim 3, wherein the first processor slots comprise 64-bit processor slots.

9. The system of claim 3, wherein the second buses comprise 32-bit buses.

10. The system of claim 3, wherein the second processors comprise 32-bit processors.

11. The system of claim 3, wherein the CEC comprises a transaction generator, wherein the transaction generator generates pseudo-random memory read and write transactions.

12. A method for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms, the method steps comprising:

setting up an initial state of a scalable symmetric multiple processor computer system;

initializing all data structures of the scalable symmetric multiple processor computer system beyond the initial state;

tracking write and read transactions issued to memory cache lines; and

comparing a listing of the initial state against a listing of a state resulting from the write and read transactions.

13. The method of claim 12, wherein the initializing step comprises assigning a unique byte address in a multiple-byte cache line to each processor operating in a scalable symmetric multiple processor computer system.

14. The method of claim 13, wherein the tracking step comprises:

determining if a memory cache transaction is a write or read transaction;

deriving an address of a write transaction;

checking if a data entry in an address list exists for the address of the write transaction;

updating the data entry in the address list if the data entry exists for the address of the write transaction; and

adding a new data entry in the address list comprising the address and data of the write transaction.

15. The method of claim 13, wherein the tracking step comprises:

determining if a memory cache transaction is a write or read transaction;

deriving an address of a read transaction;

storing the address, a transaction identifier, and a return register for the read transaction in a data entry in a transaction list;

checking an address list to determine if a write transaction has been previously executed on the address of the read transaction;

setting a valid flag in a data entry in the transaction list corresponding to the read transaction if a write transaction has been previously executed on the address of the read transaction; and

storing data from a previous write transaction into the data entry in the transaction list corresponding to the read transaction if a write transaction has been previously executed on the address of the read transaction.

16. The method of claim 15, wherein the method further comprises steps for:

checking the transaction list for the transaction identifier of a read transaction being retired;

comparing the data from the previous write transaction with the data stored in a return register specified in the transaction list data entry for that read transaction; and

reporting an error if the data from the previous write transaction differs from the data in the return register specified in the transaction list data entry for that read transaction.

17. A computer readable medium upon which is embedded instructions for carrying out a method for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms, the method steps comprising:

setting up an initial state of a scalable symmetric multiple processor computer system;

initializing all data structures of the scalable symmetric multiple processor computer system beyond the initial state;

tracking write and read transactions issued to memory cache lines; and

comparing a listing of the initial state against a listing of a state resulting from the write and read instructions.

18. The computer readable medium of claim 17, wherein the initializing step comprises assigning a unique byte address in a multiple-byte cache line to each processor operating in a scalable symmetric multiple processor computer system.

19. The computer readable medium of claim 18, wherein the tracking step comprises:

determining if a memory cache transaction is a write or read transaction;

deriving an address of a write transaction;

checking if a data entry in an address list exists for the address of the write transaction;

updating the data entry in the address list if the data entry exists for the address of the write transaction; and

adding a new data entry in the address list comprising the address and data of the write transaction.

20. The computer readable medium of claim 18, wherein the tracking step comprises:

determining if a memory cache transaction is a write or read transaction;

deriving an address of a read transaction;

storing the address, a transaction identifier, and a return register for the read transaction in a data entry in a transaction list;

checking an address list to determine if a write transaction has been previously executed on the address of the read transaction;

setting a valid flag in a data entry in the transaction list corresponding to the read transaction if a write transaction has been previously executed on the address of the read transaction;

storing data from a previous write transaction into the data entry in the transaction list corresponding to the read transaction if a write transaction has been previously executed on the address of the read transaction;

checking the transaction list for the transaction identifier of a read transaction being retired;

comparing the data from the previous write transaction with the data stored in a return register specified in the transaction list data entry for that read transaction; and

reporting an error if the data from the previous write transaction differs from the data in the return register specified in the transaction list data entry for that read transaction.