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Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms

  • US 20040210719A1
  • Filed: 05/10/2004
  • Published: 10/21/2004
  • Est. Priority Date: 11/19/2001
  • Status: Active Grant
First Claim
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1. A system for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms, the system comprising:

  • a scalable symmetric multiple processor computer system, wherein the scalable symmetric multiple processor computer system comprises;

    a central electronics complex (CEC), one or more first buses connected to the CEC, one or more first processor slots connected to the one or more first buses, and a memory;

    an application specific integrated circuit (ASIC) replacing a processor in each of the one or more first processor slots of the scalable symmetric multiple processor computer system;

    a first memory cache unit associated with each ASIC;

    one or more second buses connected to each ASIC;

    one or more second processors connected to each second bus; and

    a second memory cache unit associated with each second processor.

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