Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms
First Claim
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1. A system for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms, the system comprising:
- a scalable symmetric multiple processor computer system, wherein the scalable symmetric multiple processor computer system comprises;
a central electronics complex (CEC), one or more first buses connected to the CEC, one or more first processor slots connected to the one or more first buses, and a memory;
an application specific integrated circuit (ASIC) replacing a processor in each of the one or more first processor slots of the scalable symmetric multiple processor computer system;
a first memory cache unit associated with each ASIC;
one or more second buses connected to each ASIC;
one or more second processors connected to each second bus; and
a second memory cache unit associated with each second processor.
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Abstract
A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.
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Citations
20 Claims
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1. A system for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms, the system comprising:
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a scalable symmetric multiple processor computer system, wherein the scalable symmetric multiple processor computer system comprises;
a central electronics complex (CEC), one or more first buses connected to the CEC, one or more first processor slots connected to the one or more first buses, and a memory;
an application specific integrated circuit (ASIC) replacing a processor in each of the one or more first processor slots of the scalable symmetric multiple processor computer system;
a first memory cache unit associated with each ASIC;
one or more second buses connected to each ASIC;
one or more second processors connected to each second bus; and
a second memory cache unit associated with each second processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms, the method steps comprising:
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setting up an initial state of a scalable symmetric multiple processor computer system;
initializing all data structures of the scalable symmetric multiple processor computer system beyond the initial state;
tracking write and read transactions issued to memory cache lines; and
comparing a listing of the initial state against a listing of a state resulting from the write and read transactions. - View Dependent Claims (13, 14, 15, 16)
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17. A computer readable medium upon which is embedded instructions for carrying out a method for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms, the method steps comprising:
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setting up an initial state of a scalable symmetric multiple processor computer system;
initializing all data structures of the scalable symmetric multiple processor computer system beyond the initial state;
tracking write and read transactions issued to memory cache lines; and
comparing a listing of the initial state against a listing of a state resulting from the write and read instructions. - View Dependent Claims (18, 19, 20)
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Specification