On-board diagnostic circuit for an integrated circuit

• US 20040210797A1
• Filed: 04/17/2003
• Published: 10/21/2004
• Est. Priority Date: 04/17/2003
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Field, Ian, Kimelman, Paul
• Granted Patent: US 7,444,546 B2
• Time in Patent Office: Days
• US Class Current: 714/25
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test

Abstract

An integrated circuit having a plurality of functional circuits interconnected via a functional bus is provided with a diagnostic bus-master circuit which uses bus transactions on the functional bus to perform diagnostic operations. These diagnostic operations can be performed in real time during normal speed operation of the integrated circuit to produce more accurate diagnostic results. The diagnostic bus-master circuit is particularly useful for reading data values from memory or writing data values to memory as part of diagnostic operations.

Claims

1. An integrated circuit comprising:

a plurality of functional circuits operable to perform data processing operations;

at least one functional bus operable to provide communication between said plurality of functional circuits; and

a diagnostic bus-master circuit operable to perform a diagnostic operation upon at least one of said plurality of functional circuits by issuing a bus transaction request via said at least one functional bus to one or more of said plurality of functional circuits during real time operation of said plurality of functional circuits.

2. An integrated circuit as claimed in claim 1, wherein said diagnostic bus-master circuit is operable to perform one or more of:

debugging operations;

manufacturing test operations;

manufacturing programming operations;

manufacturing configuration operations;

field programming operations; and

field configuration operations.

3. An integrated circuit as claimed in claim 1, wherein said diagnostic bus-master circuit is operable to perform an authentication operation to authorise said diagnostic bus-master circuit to at least one of perform diagnostic operations and access said functional bus.

4. An integrated circuit as claimed in claim 3, comprising an authentication circuit connected to said at least one functional bus, said authentication operation comprising said diagnostic bus-master circuit issuing an authentication request to said authentication circuit, said authentication circuit being operable to selectively authorise said diagnostic bus-master circuit in dependence upon said authentication request matching predetermined criteria.

5. An integrated circuit as claimed in claim 1, comprising a dedicated diagnostic bus connecting said diagnostic bus-master circuit to at least one of said plurality of functional circuits, said dedicated diagnostic bus providing access to data not accessible via said at least one functional bus.

6. An integrated circuit as claimed in claim 1, comprising a plurality of functional buses having different bus protocols, said diagnostic bus-master circuit comprising a plurality of bus interface circuits each for communicating with a respective functional bus using a bus protocol for said respective functional bus.

7. An integrated circuit as claimed in claim 1, wherein said diagnostic bus-master circuit comprises an external interface circuit for communicating with respective external diagnostic devices using respective external signal protocols.

8. An integrated circuit as claimed in claim 1, wherein said diagnostic bus-master circuit is operable transfer signal between a clock domain of said integrated circuit and a clock domain of an external diagnostic device coupled to said diagnostic bus-master circuit.

9. An integrated circuit as claimed in claim 1, wherein said diagnostic bus-master circuit is operable to perform one or more of:

load data values from a device coupled said at least one functional bus;

store data values to a device coupled said at least one functional bus;

copy data values between devices coupled said at least one functional bus; and

verify data values stored in a device coupled said at least one functional bus.

10. An integrated circuit as claimed in claim 1, wherein a flash memory is coupled to said at least one functional bus and said diagnostic bus-master circuit is operable to program said flash memory using a flash memory programming protocol.

11. An integrated circuit as claimed in claim 1 wherein said integrated circuit is a system-on-chip integrated circuit.

12. An integrated circuit as claimed in claim 1, wherein said at least one functional bus is an external bus of said integrated circuit.

13. An integrated circuit as claimed in claim 1, wherein said at least one functional bus is an AMBA bus.

14. A method of performing real time diagnostic operations upon an integrated circuit having a plurality of functional circuits operable to perform data processing operations and at least one functional bus operable to provide communication between said plurality of functional circuits, said method comprising the step of issuing a bus transaction request from a diagnostic bus-master circuit via said at least one functional bus to one or more of said plurality of functional circuits during real time operation of said plurality of functional circuits.

15. A method as claimed in claim 14, wherein said diagnostic bus-master circuit is operable to perform one or more of:

debugging operations;

manufacturing test operations;

manufacturing programming operations;

manufacturing configuration operations;

field programming operations; and

field configuration operations.

16. A method as claimed in claim 14, wherein said diagnostic bus-master circuit is operable to perform an authentication operation to authorise said diagnostic bus-master circuit to at least one of perform diagnostic operations and access said functional bus.

17. A method as claimed in claim 16, wherein an authentication circuit is connected to said at least one functional bus, said authentication operation comprising said diagnostic bus-master circuit issuing an authentication request to said authentication circuit, said authentication circuit being operable to selectively authorise said diagnostic bus-master circuit in dependence upon said authentication request matching predetermined criteria.

18. A method as claimed in claim 14, wherein a dedicated diagnostic bus connects said diagnostic bus-master circuit to at least one of said plurality of functional circuits, said dedicated diagnostic bus providing access to data not accessible via said at least one functional bus.

19. A method as claimed in claim 14, wherein said integrated circuit comprises a plurality of functional buses having different bus protocols, said diagnostic bus-master circuit having a plurality of bus interface circuits each for communicating with a respective functional bus using a bus protocol for said respective functional bus.

20. A method as claimed in claim 14, wherein said diagnostic bus-master circuit comprises an external interface circuit for communicating with respective external diagnostic devices using respective external signal protocols.

21. A method as claimed in claim 14, wherein said diagnostic bus-master circuit is operable transfer signal between a clock domain of said integrated circuit and a clock domain of an external diagnostic device coupled to said diagnostic bus-master circuit.

22. A method as claimed in claim 14, wherein said diagnostic bus-master circuit is operable to perform one or more of:

load data values from a device coupled said at least one functional bus;

store data values to a device coupled said at least one functional bus;

copy data values between devices coupled said at least one functional bus; and

verify data values stored in a device coupled said at least one functional bus.

23. A method as claimed in claim 14, wherein a flash memory is coupled to said at least one functional bus and said diagnostic bus-master circuit is operable to program said flash memory using a flash memory programming protocol.

24. A method as claimed in claim 14, wherein said integrated circuit is a system-on-chip integrated circuit.

25. A method as claimed in claim 14, wherein said at least one functional bus is an internal bus of said integrated circuit.

26. A method as claimed in claim 14, wherein said at least one functional bus is an AMBA bus.