DIAGNOSTIC METHOD FOR STRUCTURAL SCAN CHAIN DESIGNS

• US 20040210808A1
• Filed: 04/16/2003
• Published: 10/21/2004
• Est. Priority Date: 04/16/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tran, Phong T., Motika, Franco, Nigh, Phillip J.
• Granted Patent: US 6,961,886 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits

Abstract

A method for testing and diagnosing shift register latch chains coupled to logic circuits in an integrated circuit, the method including: (a) determining which of the shift register latch chains are failing by propagating a test pattern of zeros and ones through the shift register latch chains while gating which of the shift register latch chains contents are propagated into the means for generating a test signature; and (b) for each failing shift register latch chain: (b1) propagating a test pattern through the shift register latch chains while gating a selected sequential group of latches in a failing shift register latch to propagate into the means for generating a test signature; (b2) reducing the number of latches in the sequential group of latches; and (b3) repeating steps (b1) and (b2) until all failing latches of the failing shift register latch chain have been determined.

Claims

1. An integrated circuit comprising:

logic circuits connected to a shift register latch chain, said shift register latch chain comprising shift register latches;

means for propagating a test pattern in said shift register latch chain through said logic circuits and into means for generating a test signature based on a response of said logic circuits to said test pattern, said test pattern supplied from a source external to said integrated circuit;

means for selectively gating the contents of said shift registers into said means for generating said test signature based upon selected test patterns; and

means for gating the contents of a sequential group of shift register latches into said means for generating said test signature based upon a specified range of SRL chain load/unload cycles, said range of SRL chain load/unload cycles determined by a selectable start and a selectable stop count.

2. The integrated circuit of claim 1:

wherein said shift register latch chain is divided into sub-shift register latch chains; and

said integrated circuit further including means for gating the contents of shift register latches in one or more sub-shift register chains into said means for generating said test signature.

3. The integrated circuit of claim 2, further including means for inverting or not inverting the contents of each shift register latch in said sub-shift register latch chains before propagating the contents of each shift register latch into said means for generating said test signature.

4. The integrated circuit of claim 1, further including means for gating the contents of shift register latches in a range of shift register latches which is responsive to a sub-shift register latch chain load/unload shift count parameter, said means for gating the contents of shift register latches based upon a range of load/unload cycles is responsive to a pattern cycle control parameter and said means for gating the contents of shift register latches in one or more sub-shift register chains is responsive to a sub-shift register latch chain to means for generating a test signature selection parameter.

5. The integrated circuit of claim 1, further including means for inverting or not inverting the contents of each shift register latch in said shift register latch chain before propagating the contents of each shift register latch into said means for generating said test signature.

6. The integrated circuit of claim 1 , wherein said source supplying said test pattern is a external tester or an external pseudo random pattern generator.

7. A method of testing and diagnosing an integrated circuit comprising:

providing logic circuits connected to a shift register latch chain, said

shift register latch chain comprised of shift register latches;

providing means for propagating a test pattern in said shift register latch chain through said logic circuits and into means for generating a test signature based a response of said logic circuits to said test pattern, said test pattern supplied from a source external to said integrated circuit; and

selectively gating the contents of said shift registers into said means for generating said test signature based upon selected test patterns.

8. The method of claim 7, further including, gating the contents of a sequential group of shift register latches into said means for generating said test signature based upon a specified range of SRL chain load/unload cycles, said range of SRL chain load/unload cycles determined by a selectable start and a selectable stop count.

9. The method of claim 7:

wherein said shift register latch chain is divided into sub-shift register latch chains; and

said method further including gating the contents of shift register latches in one or more sub-shift register chains into said means for generating said test signature.

10. The method of claim 9, further including inverting or not inverting the contents of each shift register latch in said sub-shift register latch chains before propagating the contents of each shift register latch into said means for generating said test signature.

11. The method of claim 7, further including inverting or not inverting the contents of each shift register latch in said shift register latch chain before propagating the contents of each shift register latch into said means for generating said test signature.

12. The method of claim 7, said source supplying said test pattern is a external tester or an external pseudo random pattern generator.

13. A method for testing and diagnosing broken or stuck-at shift register latch chains comprised of shift register latches, said shift register latch chains coupled to logic circuits in an integrated circuit, the method comprising in the order listed:

(a) determining which of said shift register latch chains are failing by propagating a first test pattern of zeros and ones through said shift register latch chains while gating which of said shift register latch chains contents are propagated into said means for generating a test signature, said determination of failing shift register latch chains made on the basis of said test signature; and

(b) for each failing shift register latch chain;

(b1) propagating a second test pattern through said shift register latch chains while allowing only the contents of a selected sequential group of shift register latches in a failing shift register latch to propagate into said means for generating a test signature;

(b2) reducing the number of shift register latches in said sequential group of shift register latches; and

(c3) repeating steps (b1) and (b2) until all failing shift register latches of the failing shift register latch chain have been determined, said determination of failing shift register latches made on the basis of said test signature.

14. The method of claim 13, further including before step (a) propagating a test pattern of zeros and ones through said shift register latch chains without propagating said test pattern through said logic circuits in order to test logic built-in self-test circuits coupled to said logic circuits and to said shift-register latch chains.

15. The method of claim 13, wherein step (a) is performed twice in immediate succession, the second performance of step (a) further including inverting the contents of said shift register latch chains before propagation of the contents of said shift register latch chains into said means for generating a test signature.

16. The method of claim 13, wherein step (b1) further includes inverting the contents of said range of shift register latches in a failing shift register latch before propagating said contents of said range of shift register latches into said means for generating a test signature.

17. The method of claim 13, wherein step (b2) includes performing a linear reduction algorithm or performing a binary reduction algorithm.

18. The method of claim 13, wherein said first and second test patterns are generated from a tester external to said integrated circuit, a pseudo random pattern generator external to said integrated circuit or a logic built-in self-test circuit internal to said integrated circuit.

19. The method of claim 15, wherein step (b1) includes loading a predetermined pattern into said means for generating a test signature prior to said propagating said second test pattern through said shift register latch chains in order to determine if said integrated circuit is failing.

20. The method of claim 13, wherein said second test pattern is all zeros or all ones.