InGaAs/GaAs high electron mobility transistor

• US 20040211955A1
• Filed: 03/08/2004
• Published: 10/28/2004
• Est. Priority Date: 04/25/2003
• Status: Active Grant

• Current Assignee: National Cheng KUNG University (Government of The Republic of China)
• Original Assignee: National Cheng KUNG University (Government of The Republic of China)
• Inventors: Lee, Ching-Sung, Hsu, Wei-Chou
• Granted Patent: US 6,953,955 B2
• Time in Patent Office: Days
• US Class Current: 257/20
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7784 with delta or planar doped donor layer H01L29/7785 takes precedence

Abstract

An InGaAs/GaAs High Electron Mobility Transistor (HEMT) comprises a buffer layer, a main conducting channel, an InGaAs/GaAs thickness-graded superlattice structure, a mono atom δ-doped carrier supply layer, a Schottky cap layer of gate electrode and an Ohmic cap layer of drain electrode and source electrode which are formed successively on a substrate. The superlattice structure comprises spacer and sub-channel. By using thickness-graded superlattice spacer structure is able to ameliorate lattice-mismatch-induced scattering within heterostucture interfacial, increase range of gate voltage swing in gate electrode, and through real-space transfer generated by bias voltage in high electric field, drain-to-source saturation current proceed step-up phenomenon to forming a HEMT having scalable voltage multi-extrinsic transconductance enhanced portions.

Claims

1. An InGaAs/GaAs high electron mobility transistor (HEMT) comprising:

a substrate;

a buffer layer overlying said substrate;

a main conducting channel overlying said buffer layer;

a thickness-graded superlattice structure overlying said main conducting channel to form spacer and sub-channel;

a mono atom δ

-doped carrier supply layer overlying said thickness-graded superlattice structure;

a Schottky cap layer of gate electrode overlying said mono atom δ

-doped carrier supply layer; and

an Ohmic cap layer of drain electrode and source electrode overlying said Schottky cap layer of gate electrode.

2. The transistor according to claim 1, wherein said substrate is a GaAs.

3. The transistor according to claim 1, wherein said buffer layer is an undoped GaAs with a thickness in the range of 0.1 to 5.0 micro meters.

4. The transistor according to claim 1, wherein said main conducting channel is an undoped InGaAs having general form In_xGa₁₋

xAs with a thickness in the range of 60 to 100 Angstroms, wherein x is in the range of 0 to 0.3.

5. The transistor according to claim 1, wherein said spacer is an undoped GaAs having a thickness in the range of 10 to 50 Angstroms, and said sub-channel is an undoped InGaAs having a thickness in the range of 5 to 35 Angstroms and a general form In_xGa₁₋

xAs, wherein x is in the range of 0 to 0.3.

6. The transistor according to claim 1, wherein said thickness-graded superlattice structure has a total thickness in the range of 20 to 300 Angstroms.

7. The transistor according to claim 1, wherein said mono atom δ

-doped carrier supply layer has a concentration in the range of δ

(n)=1×

10¹¹˜

1×

10¹³ cm<sup>−

2</sup>.

8. The transistor according to claim 1, wherein Schottky cap layer of gate electrode is an undoped GaAs with a thickness of 100 Angstroms to 1 micro meter.

9. The transistor according to claim 1, wherein said Schottky cap layer of gate electrode is an undoped InGaP having a general form as In_xGa₁₋

xP with a thickness in the range of 100 Angstroms to 1 micro meter, wherein x is in the range of 0.48 to 0.51,

10. The transistor according to claim 1, wherein top of said Ohmic cap layer of drain electrode and source electrode is an undoped GaAs having a thickness in the range of 100 Angstroms to 1 micro meter.

11. The transistor according to claim 1, wherein top of said Ohmic cap layer of drain electrode and source electrode is a n-type GaAs having a thickness in the range of 100 Angstroms to 1 micro meter and a concentration in the range of n=1×

10¹⁸˜

1×

10¹⁹ cm<sup>−

3</sup>.

12. The transisitor according to claim 1, wherein said transistor form being selected from the group consisting of Metal-Organic Chemical Vapor Deposition (MOCVD) and Molecular Beam Epitaxy (MBE).

13. The transistor according to claim 1, wherein said gate electrode is a gold (Au) with a thickness in the range of 100 Angstroms to 1 micro meter.

14. The transistor according to claim 1, wherein said drain electrode and source electrode is a Ag/AuGe/Ni with a total thickness in the range of 200 Angstroms to 1 micro meter.

15. The transistor according to claim 1, wherein said drain electrode and source electrode form Ohmic contact with said main conducting channel by using quenching of temperature in the range of 300 to 500 Celsius.