Compound semiconductor FET

• US 20040211976A1
• Filed: 01/23/2004
• Published: 10/28/2004
• Est. Priority Date: 04/28/2003
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Twynam, John
• Granted Patent: US 7,538,364 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

On a substrate of a GaN FET, an undoped AlN layer, a GaN delta doped layer, an undoped GaN layer, and an undoped Al_0.2Ga_0.8N layer are formed in sequence. Arranged on the undoped Al_0.2Ga_0.8N layer are a Ti/Al/Pt/Au source ohmic electrode, a Pt/Au gate Schottky electrode, and a Ti/Al/Pt/Au drain ohmic electrode. Parallel conduction and gate leak are reduced or eliminated by the GaN delta doped layer.

Claims

1. A compound semiconductor FET comprising:

an AlN layer provided on a substrate;

an n-type delta doped 11′

-N layer provided on the AlN layer;

a plurality of III-N layers provided on the n-type delta doped III-N layer;

a source electrode;

a gate electrode; and

a drain electrode.

2. The compound semiconductor FET according to claim 1, wherein the n-type delta doped III-N layer is an n-type delta doped GaN layer,

wherein the plurality of III-N layers comprise a GaN layer and an AlGaN layer formed on the GaN layer, and

wherein the source electrode, the gate electrode, and the drain electrode are provided on the AlGaN layer.

3. The compound semiconductor FET according to claim 1, further comprising an insulating layer on the AlGaN layer, wherein the n-type delta doped III-N layer is an n-type delta doped GaN layer,

wherein the plurality of III-N layers comprise a GaN layer and an AlGaN layer formed on the GaN layer,

wherein the source electrode and the drain electrode are provided on the AlGaN layer, and

wherein the gate electrode is provided on the insulating layer.

4. The compound semiconductor FET according to claim 1, wherein dopant concentration of the n-type delta doped III-N layer is set so as to reduce discontinuity of an electric field at an interface between the AlN layer and the III-N layer.

5. The compound semiconductor FET according to claim 1, wherein material of the substrate is sapphire,

wherein each of the semiconductor layers is formed of a semiconductor having a C-plane Ga-surface, and

wherein sheet doping concentration of the n-type delta doped III-N layer is within a range of 1×

10¹³ cm<sup>−

2</sup> to 2×

10¹³ cm<sup>−

2</sup>.

6. The compound semiconductor FET according to claim 1, wherein material of the substrate is SiC,

wherein each of the semiconductor layers is formed of a C-plane Ga-surface oriented semiconductor, and

wherein sheet doping concentration of the n-type delta doped III-N layer is within a range of 5×

10¹² cm<sup>−

2</sup> to 1.5×

10¹³ cm<sup>−

2</sup>.

7. An electronic circuit provided with the compound semiconductor FET as defined in claim 1.