Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same

• US 20040211980A1
• Filed: 04/24/2003
• Published: 10/28/2004
• Est. Priority Date: 04/24/2003
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Ryu, Sei-Hyung
• Granted Patent: US 7,074,643 B2
• Time in Patent Office: Days
• US Class Current: 257/200
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region or a first conductivity type, a buried silicon carbide region of a second conductivity type opposite to the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer. The source region and the buried silicon carbide region are formed utilizing a first window of the mask layer. Then, the well region is formed utilizing a second window of the mask layer, the second window being provided by a subsequent etch of the mask layer having the first window.

Claims

1. A method of fabricating a silicon carbide power device comprising:

successively patterning a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region of a second conductivity type opposite the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer.

2. The method of claim 1, further comprising:

forming the source region and the buried silicon carbide region utilizing a first window of the mask layer; and

then

forming the well region utilizing a second window of the mask layer, the second window being provided by a subsequent patterning of the mask layer having the first window.

3. The method of claim 1, wherein the first conductivity type is n-type silicon carbide and the second conductivity type is p-type silicon carbide and wherein the buried silicon carbide region comprises a buried p-type silicon carbide region and the well region comprises a p-well region.

4. The method of claim 3, wherein successively patterning a mask layer, forming the source region and the buried p-type silicon carbide region and forming the p-well region comprise:

forming the mask layer on a first surface of the first n-type silicon carbide layer;

patterning the mask layer to provide a first implantation mask, the first implantation mask having at least one window corresponding to the source region of the silicon carbide power device;

then

implanting n-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask to provide an n-type source region, the n-type source region extending to the first surface of the first n-type silicon carbide layer and having a higher carrier concentration than the first n-type silicon carbide layer;

implanting p-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask to provide the buried p-type region adjacent the n-type source region, the buried p-type region being disposed at a depth in the first n-type silicon carbide layer greater than a depth of the n-type source region;

then

isotropically etching the first implantation mask to provide a second implantation mask, the second implantation mask having at least one window corresponding to the p-well region and corresponding to the at least one window of the first implantation mask widened by the isotropic etch; and

then

implanting p-type dopants in the first n-type silicon carbide layer utilizing the second implantation mask to provide the p-well region, the p-well region extending to the p-type buried region.

5. The method of claim 3, wherein successively patterning a mask layer to provide windows for formation of a source region, a buried p-type silicon carbide region and a p-well region comprises successively patterning a mask layer to provide windows for formation of a source region, a buried p-type silicon carbide region, a p-well region and a threshold adjustment region in a first n-type silicon carbide layer, the method further comprising forming the threshold adjustment region utilizing a third window of the mask layer, the third window being provided by a subsequent etch of the mask layer having the second window.

6. The method of claim 3, wherein successively patterning a mask layer, forming the source region and the buried p-type silicon carbide region and forming the p-well region comprise:

forming the mask layer on a first n-type silicon carbide layer;

patterning the mask layer to provide a first implantation mask, the first implantation mask having at least one window corresponding to the source region of the silicon carbide power device;

then

implanting n-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask to provide an n-type source region, the n-type source region extending to a first surface of the first n-type silicon carbide layer and having a higher carrier concentration than the first n-type silicon carbide layer;

implanting p-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask to provide the buried p-type region adjacent the n-type source region, the p-type dopants being implanted utilizing a higher implantation energy than an implant energy utilized to implant the n-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask to provide an n-type source region;

then

isotropically etching the first implantation mask to provide a second implantation mask, the second implantation mask having at least one window corresponding to the p-well region and corresponding to the at least one window of the first implantation mask widened by the isotropic etch; and

then

implanting p-type dopants in the first n-type silicon carbide layer utilizing the second implantation mask to provide the p-well region, the p-type dopants being implanted utilizing an implantation energy such that the p-well region extends to the p-type buried region.

7. The method of claim 6, wherein implanting p-type dopants in the first n-type silicon carbide layer utilizing the second implantation mask to provide the p-well region comprises implanting p-type dopants in-the first n-type silicon carbide layer utilizing the second implantation mask to provide a carrier concentration of the p-well region that is less than a carrier concentration of the buried p-type silicon carbide layer.

8. The method of claim 5, wherein implanting p-type dopants in the first n-type silicon carbide layer utilizing the second implantation mask to provide the p-well region is followed by:

isotropically etching the second implantation mask to provide a third implantation mask, the third implantation mask having at least one window corresponding to a threshold adjustment region and corresponding to the at least one window of the second implantation mask widened by the isotropic etch; and

then

implanting n-type dopants in the first n-type silicon carbide layer utilizing the third implantation mask to provide the threshold adjustment region.

9. The method of claim 8, wherein implanting n-type dopants in the first n-type silicon carbide layer utilizing the third implantation mask to provide the threshold adjustment region comprises implanting n-type dopants in the first n-type silicon carbide layer utilizing the third implantation mask to a depth of from about 0.01 to about 0.5 μ

m into the first n-type silicon carbide layer.

10. The method of claim 8, further comprising:

removing the third implantation mask;

forming a fourth implantation mask, the fourth implantation mask patterned to provide a window exposing the first surface of the first n-type silicon carbide layer inside the source region;

implanting p-type dopants utilizing the fourth implantation mask to provide a p-type silicon carbide plug region, the plug region extending into the first n-type silicon carbide layer to contact the p-type buried region;

forming a gate oxide on the first surface of the first n-type silicon carbide layer;

forming a gate contact on the gate oxide;

forming a source contact on the source region and the plug region and forming a drain contact on the first n-type silicon carbide layer opposite the first surface.

11. The method of claim 10, further comprising forming a second n-type silicon carbide layer on a surface of the first n-type silicon carbide layer opposite the first surface, the second n-type silicon carbide layer having a carrier concentration higher than a carrier concentration of the first n-type silicon carbide layer.

12. The method of claim 8, wherein implanting n-type dopants in the first n-type silicon carbide layer utilizing the third implantation mask to provide the threshold adjustment region is followed by:

removing the third implantation mask; and

forming an n-type silicon carbide epitaxial layer on the first surface of the first n-type silicon carbide layer.

13. The method of claim 12, wherein forming an n-type silicon carbide epitaxial layer is preceded by the steps of:

forming a fourth implantation mask, the fourth implantation mask patterned to provide a window exposing a portion of the n-type silicon carbide epitaxial layer inside the source region;

implanting p-type dopants utilizing the fourth implantation mask to provide a p-type silicon carbide plug region, the plug region extending into the first n-type silicon carbide layer to contact the p-type buried region; and

activating the implanted dopants; and

wherein forming an n-type silicon carbide epitaxial layer is followed by the steps of;

forming a gate oxide on n-type silicon carbide epitaxial layer;

forming a gate contact on the gate oxide;

forming a source contact on the source region and the plug region; and

forming a drain contact on the first n-type silicon carbide layer opposite the first surface.

14. The method of claim 13, further comprising forming a second n-type silicon carbide layer on a surface of the first n-type silicon carbide layer opposite the first surface, the second n-type silicon carbide layer having a carrier concentration higher than a carrier concentration of the first n-type silicon carbide layer.

15. The method of claim 5, wherein implanting p-type dopants in the first n-type silicon carbide layer utilizing the second implantation mask to provide the p-well region is followed by:

removing the second implantation mask; and

forming an n-type silicon carbide epitaxial layer on the first surface of the first n-type silicon carbide layer.

16. The method of claim 15, wherein forming an n-type silicon carbide epitaxial layer is preceded by the steps of:

forming a third implantation mask, the third implantation mask patterned to provide a window exposing a portion of the n-type silicon carbide epitaxial layer inside the source region;

implanting p-type dopants utilizing the third implantation mask to provide a p-type silicon carbide plug region, the plug region extending into the first n-type silicon carbide layer to contact the p-type buried region; and

activating the implanted dopants; and

wherein forming an n-type silicon carbide epitaxial layer is followed by the steps of;

forming a gate oxide on n-type silicon carbide epitaxial layer;

forming a gate contact on the gate oxide;

forming a source contact on the source region and the plug region; and

forming a drain contact on the first n-type silicon carbide layer opposite the first surface.

17. The method of claim 16, further comprising forming a second n-type silicon carbide layer on a surface of the first n-type silicon carbide layer opposite the first surface, the second n-type silicon carbide layer having a carrier concentration higher than a carrier concentration of the first n-type silicon carbide layer.