SILICON CARBIDE MOSFETS WITH INTEGRATED ANTIPARALLEL JUNCTION BARRIER SCHOTTKY FREE WHEELING DIODES AND METHODS OF FABRICATING THE SAME

• US 20040212011A1
• Filed: 04/24/2003
• Published: 10/28/2004
• Est. Priority Date: 04/24/2003
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Ryu, Sei-Hyung
• Granted Patent: US 6,979,863 B2
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices have a silicon carbide DMOSFET and an integral silicon carbide Schottky diode configured to at least partially bypass a built in diode of the DMOSFET. The Schottky diode may be a junction barrier Schottky diode and may have a turn-on voltage lower than a turn-on voltage of a built-in body diode of the DMOSFET. The Schottky diode may have an active area less than an active area of the DMOSFET.

Claims

1. A silicon carbide semiconductor device, comprising:

a silicon carbide DMOSFET; and

an integral silicon carbide Schottky diode configured to have a turn-on voltage lower than a turn-on voltage of a built-in body diode of the DMOSFET.

2. The silicon carbide semiconductor device of claim 1, wherein the integral silicon carbide Schottky diode comprises an integral silicon carbide junction barrier Schottky (JBS) diode.

3. The silicon carbide semiconductor device of claim 2, wherein the integral JBS diode has a turn-on voltage of about 1 volt.

4. The silicon carbide semiconductor device of claim 1, wherein the silicon carbide Schottky diode comprises:

a Schottky contact adjacent and coupled to the source region;

a drift region common with a drift region of the DMOSFET; and

a second contact common with a drain contact of the DMOSFET.

5. The silicon carbide semiconductor device of claim 4, wherein the silicon carbide Schottky diode further comprises a p-type junction barrier Schottky (JBS) grid adjacent a source region of the DMOSFET.

6. The silicon carbide semiconductor device of claim 5, wherein a p-type region of the JBS grid has an ohmic contact to a source electrode of the DMOSFET and contacts a p-type well region of the DMOSFET.

7. The silicon carbide semiconductor device of claim 4, wherein the Schottky contact is in direct contact with the source region.

8. The silicon carbide semiconductor device of claim 4, wherein the Schottky contact is coupled to the source region through a source contact of the DMOSFET.

9. The silicon carbide semiconductor device of claim 2, wherein an active area of the integral silicon carbide JBS diode is less than the active area of the silicon carbide DMOSFET.

10. The silicon carbide semiconductor device of claim 2, wherein the active area of the integral silicon carbide JBS diode is less than about 50% the active area of the silicon carbide DMOSFET.

11. The silicon carbide semiconductor device of claim 2, wherein the active area of the integral silicon carbide JBS diode is less than about 25% the active area of the silicon carbide DMOSFET.

12. The silicon carbide semiconductor device of claim 2, wherein the active area of the integral silicon carbide JBS diode is less than about 20% the active area of the silicon carbide DMOSFET.

13. The silicon carbide semiconductor device of claim 2, wherein the active area of the integral silicon carbide JBS diode is selected to flow a full switch current of the DMOSFET at a bias voltage of less than or equal to 2.6 V.

14. A silicon carbide semiconductor device, comprising:

a first n-type silicon carbide layer;

a p-type silicon carbide well region in the first n-type silicon carbide layer and extending to a first surface of the first n-type silicon carbide layer;

a second n-type silicon carbide layer in the first n-type silicon carbide layer adjacent a portion of p-type silicon carbide well region, the second n-type silicon carbide layer extending to the first surface of the first n-type silicon carbide layer and having a carrier concentration that is higher than a carrier concentration of the first n-type silicon carbide layer;

a gate insulator layer on the first n-type silicon carbide layer, the second n-type silicon carbide layer and the p-type silicon carbide well region;

a plurality of spaced apart p-type silicon carbide regions in the first n-type silicon carbide to provide a junction barrier grid, a peripheral one of the plurality of spaced apart p-type silicon carbide regions is adjacent the second n-type silicon carbide region and the p-type silicon carbide well region;

a Schottky contact on the first n-type silicon carbide layer and the plurality of p-type silicon carbide regions;

a source contact adjacent the Schottky contact and on the second n-type silicon carbide layer;

a gate contact on the gate insulator layer; and

a drain contact on the first n-type silicon carbide layer opposite the first surface of the first n-type silicon carbide layer.

15. The silicon carbide semiconductor device of claim 14, further comprising a third n-type silicon carbide layer disposed between the drain contact and the first n-type silicon carbide layer, the third n-type silicon carbide layer having a carrier concentration higher than a carrier concentration of the first n-type silicon carbide layer.

16. The silicon carbide semiconductor device of claim 14, further comprising a metal overlay on the source contact and the Schottky contact so as to connect the source contact to the Schottky contact.

17. The silicon carbide semiconductor device of claim 14, wherein the peripheral one of the plurality of p-type silicon carbide regions contacts the p-type silicon carbide well region and wherein the source contact is also on a portion of the peripheral one of the plurality of p-type silicon carbide regions.

18. The silicon carbide semiconductor device of claim 17, wherein the plurality of spaced apart p-type silicon carbide regions have a higher doping concentration than a doping concentration of the p-type silicon carbide well region.

19. The silicon carbide semiconductor device of claim 14, wherein the Schottky contact, the plurality of spaced apart p-type silicon carbide regions, the first n-type silicon carbide layer and the drain contact provide a Schottky diode having a turn-on voltage less than a turn-on voltage of a built-in pn junction of the first n-type layer of silicon carbide and the p-type well region.

20. The silicon carbide semiconductor device of claim 14, wherein the first n-type silicon carbide layer has a doping concentration of from about 5×

10¹⁴ to about 2×

10¹⁶ cm<sup>−

3</sup>.

21. The silicon carbide semiconductor device of claim 14, wherein the first n-type silicon carbide layer has a thickness of from about 5 to about 30 μ

m.

22. The silicon carbide semiconductor device of claim 14, wherein the p-type silicon carbide well region has a doping concentration of from about 10¹⁶ to about 10²⁰ cm⁻

3.

23. The silicon carbide semiconductor device of claim 14, wherein the p-type silicon carbide well region extends to a depth of from about 0.5 to about 1.5 μ

m into the first n-type silicon carbide layer.

24. The silicon carbide semiconductor device of claim 14, wherein the plurality of spaced apart p-type silicon carbide regions have a doping concentration of from about 10¹⁸ to about 10²⁰ cm⁻

3.

25. The silicon carbide semiconductor device of claim 14, wherein the plurality of spaced apart p-type silicon carbide regions are spaced apart a distance of from about 0.5 to about 10 μ

m.

26. The silicon carbide semiconductor device of claim 14, wherein the plurality of spaced apart p-type silicon carbide regions are uniformly spaced apart.

27. The silicon carbide semiconductor device of claim 14, wherein the plurality of spaced apart p-type silicon carbide regions are non-uniformly spaced apart.

28. The silicon carbide semiconductor device of claim 14, wherein the plurality of spaced apart p-type silicon carbide regions have respective widths of from about 0.5 to about 10 μ

m.

29. The silicon carbide semiconductor device of claim 14, wherein the second n-type silicon carbide layer has a doping concentration of from about 10¹⁹ to about 10²¹ cm⁻

3.

30. The silicon carbide semiconductor device of claim 14, wherein the second n-type silicon carbide layer extends to a depth of from about 0.1 to about 0.7 μ

m into the first n-type silicon carbide layer.

31. A silicon carbide semiconductor device, comprising:

a silicon carbide DMOSFET; and

means for at least partially bypassing a built-in pn junction diode between a well region and a drift region of the DMOSFET when a negative voltage is applied to a drain of the DMOSFET, the means for at least partially bypassing being integral to the silicon carbide DMOSFET.

32. The silicon carbide semiconductor device according to claim 31, wherein the means for at least partially bypassing comprises an integral silicon carbide diode between a source contact and a drain contact of the DMOSFET, the integral silicon carbide diode having a lower turn-on voltage than the built-in pn junction diode.

33. The silicon carbide semiconductor device according to claim 32, wherein the integral silicon carbide diode comprises a Schottky diode.

34. The silicon carbide semiconductor device according to claim 33, wherein the Schottky diode comprises a junction barrier Schottky diode.

35. The silicon carbide semiconductor device according to claim 31, wherein the means for at least partially bypassing comprises means for completely bypassing a built-in pn junction diode between a well region and a drift region of the DMOSFET when a negative voltage is applied to a drain of the DMOSFET, the means for completely bypassing being integral to the silicon carbide DMOSFET.

36. A method of fabricating a silicon carbide semiconductor device, comprising:

forming a silicon carbide DMOSFET; and

forming an integral silicon carbide Schottky diode configured to have a turn-on voltage lower than a turn-on voltage of a built-in body diode of the DMOSFET.

37. The method of claim 36, wherein forming an integral silicon carbide Schottky diode comprises forming an integral silicon carbide junction barrier Schottky (JBS) diode.

38. The method of claim 37, wherein forming an integral JBS diode comprises forming an integral JBS diode having a turn-on voltage of about 1 volt.

39. The method of claim 36, wherein forming a silicon carbide Schottky diode comprises:

forming a Schottky contact adjacent and coupled to the source region;

forming a drift region common with a drift region of the DMOSFET; and

forming a second contact common with a drain contact of the DMOSFET.

40. The method of claim 39, wherein forming a silicon carbide Schottky diode further comprises forming a p-type junction barrier Schottky (JBS) grid adjacent a source region of the DMOSFET.

41. The method of claim 40, wherein forming a p-type JBS grid a p-type region of the JBS grid has an ohmic contact to a source electrode of the DMOSFET and contacts a p-type well region of the DMOSFET.

42. The method of claim 39, wherein forming a Schottky contact comprises forming a Schottky contact in direct contact with the source region.

43. The method of claim 39, wherein forming a Schottky contact comprises forming a Schottky contact that is coupled to the source region through a source contact of the DMOSFET.

44. The method of claim 37, wherein forming a silicon carbide JBS diode comprises forming an integral silicon carbide JBS diode having an active area that is less than the active area of the silicon carbide DMOSFET.

45. The method of claim 37, wherein forming a silicon carbide JBS diode comprises forming an integral silicon carbide JBS diode having an active area that is less than about 50% the active area of the silicon carbide DMOSFET.

46. The method of claim 37, wherein forming a silicon carbide JBS diode comprises forming an integral silicon carbide JBS diode having an active area that is less than about 25% the active area of the silicon carbide DMOSFET.

47. The method of claim 37, wherein forming a silicon carbide JBS diode comprises forming an integral silicon carbide JBS diode having an active area that is less than about 20% the active area of the silicon carbide DMOSFET.

48. A method of fabricating a silicon carbide semiconductor device, comprising:

forming a first n-type silicon carbide layer;

forming a p-type silicon carbide well region in the first n-type silicon carbide layer and extending to a first surface of the first n-type silicon carbide layer;

forming a second n-type silicon carbide layer in the first n-type silicon carbide layer adjacent a portion of p-type silicon carbide well region, the second n-type silicon carbide layer extending to the first surface of the first n-type silicon carbide layer and having a carrier concentration that is higher than a carrier concentration of the first n-type silicon carbide layer;

forming a gate insulator layer on the first n-type silicon carbide layer, the second n-type silicon carbide layer and the p-type silicon carbide well region;

forming a plurality of spaced apart p-type silicon carbide regions in the first n-type silicon carbide to provide a junction barrier grid, a peripheral one of the plurality of spaced apart p-type silicon carbide regions is adjacent the second n-type silicon carbide region and the p-type silicon carbide well region;

forming a Schottky contact on the first n-type silicon carbide layer and the plurality of p-type silicon carbide regions;

forming a source contact adjacent the Schottky contact and on the second n-type silicon carbide layer;

forming a gate contact on the gate insulator layer; and

forming a drain contact on the first n-type silicon carbide layer opposite the first surface of the first n-type silicon carbide layer.

49. The method of claim 48, further comprising forming a third n-type silicon carbide layer disposed between the drain contact and the first n-type silicon carbide layer, the third n-type silicon carbide layer having a carrier concentration higher than a carrier concentration of the first n-type silicon carbide layer.

50. The method of claim 48, further comprising forming a metal overlay on the source contact and the Schottky contact so as to connect the source contact to the Schottky contact.

51. The method of claim 48, wherein forming a plurality of spaced apart p-type silicon carbide regions comprises forming a plurality of spaced apart p-type silicon carbide regions such that the peripheral one of the plurality of p-type silicon carbide regions contacts the p-type silicon carbide well region and wherein forming a source contact further comprises forming a source on a portion of the peripheral one of the plurality of p-type silicon carbide regions.

52. The method of claim 51, wherein the plurality of spaced apart p-type silicon carbide regions have a higher doping concentration than a doping concentration of the p-type silicon carbide well region.

53. The method of claim 48, wherein the Schottky contact, the plurality of spaced apart p-type silicon carbide regions, the first n-type silicon carbide layer and the drain contact are formed to provide a Schottky diode having a turn-on voltage less than a turn-on voltage of a built-in pn junction of the first n-type layer of silicon carbide and the p-type well region.