Method to prevent die attach adhesive contamination in stacked chips

• US 20040212082A1
• Filed: 05/24/2004
• Published: 10/28/2004
• Est. Priority Date: 09/21/2000
• Status: Active Grant

• Current Assignee: Jicheng Yang
• Original Assignee: Jicheng Yang
• Inventors: Yang, Jicheng
• Granted Patent: US 7,224,070 B2
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/26145 Flow barriers
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/27013 for holding or confining the layer connector, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/29012 in top view
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83051 Forming additional members, e.g. dam structures
• CPC Class Codes: H01L 2224/83139 Guiding structures on the body
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/8592 : Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

The present invention provides methods and apparatus related to preventing adhesive contamination of the electrical contacts of a semiconductor device in a stacked semiconductor device package. The methods and apparatus include providing a first semiconductor device with an adhesive flow control dam located on an upper surface thereof. The dam is positioned between electrical contacts and a substrate attach site on the upper surface of the first semiconductor device. The dam is rendered of a sufficient height and shape to block applied adhesive from flowing over the electrical contacts of the first semiconductor device when a second substrate is mounted onto the upper surface of the first semiconductor device. The semiconductor device package may be encapsulated with the dam in place or with the dam removed. The adhesive flow control dam thus protects the electrical contacts of the first semiconductor device from contamination by excess adhesive, which can result in unusable electrical contacts.

Claims

1. A stacked semiconductor die assembly comprising:

a first semiconductor die, said first semiconductor die having an upper surface, said upper surface comprising at least one electrical contract and at least one region for mounting a second semiconductor die;

at least one adhesive flow control dam for preventing flow of an adhesive onto said at least one electrical contact during mounting of a second semiconductor die, said at least one adhesive flow control dam positioned between said at least one region for mounting a second semiconductor die and said at least one electrical contact; and

a second semiconductor die, said second semiconductor die adhesively mounted onto said at least one region for mounting a second semiconductor die of said first semiconductor die.

2. The stacked semiconductor die assembly of claim 1, further comprising an encapsulant surrounding at least a portion of a surface area of said first semiconductor die and said second semiconductor die.

3. The stacked semiconductor die assembly of claim 1, further comprising a carrier substrate, said first semiconductor die being disposed on said carrier substrate.

8. The stacked semiconductor die assembly of claim 1, wherein said at least one adhesive flow control dam comprises at least one decoupling capacitor coupon.

9. The stacked semiconductor die assembly of claim 8, wherein an adhesive used to mount said second semiconductor die includes an electrically insulating adhesive.

10. The stacked semiconductor die assembly of claim 1, wherein said at least one adhesive flow control dam comprises a material selected from a group consisting of polyimides, polyamides, and epoxies.

11. The stacked semiconductor die assembly of claim 1, wherein said at least one adhesive flow control dam includes a flow control dam more viscous than an adhesive used to adhesively mount said second semiconductor die.

12. The stacked semiconductor die assembly of claim 1, wherein said first semiconductor die is larger than said second semiconductor die.

13. The stacked semiconductor die assembly of claim 1, wherein said first semiconductor die is substantially the same size as said second semiconductor die.

14. The stacked semiconductor die assembly of claim 1, wherein said first semiconductor die comprises an integrated circuit semiconductor die.

15. The stacked semiconductor die assembly of claim 1, wherein said second semiconductor die comprises an integrated circuit semiconductor die.

16. The stacked semiconductor die assembly of claim 14, wherein said integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.

17. The stacked semiconductor die assembly of claim 15, wherein said integrated circuit semiconductor die is selected from the group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, active pixel sensor, and operation amplifier.

18. The stacked semiconductor die assembly of claim 1, wherein said first semiconductor die comprises an interposer.

19. The stacked semiconductor die assembly of claim 1, wherein said second semiconductor die is mounted in an offset fashion relative to said first semiconductor die.

20. The stacked semiconductor die assembly of claim 1, wherein at least a portion of said second semiconductor die is in contact with said at least one adhesive flow control dam.

21. The stacked semiconductor die assembly of claim 20, wherein said at least one adhesive flow control dam is configured to deform upon said contact with said second semiconductor die.

22. The stacked semiconductor die assembly of claim 1, wherein said at least one adhesive flow control dam extends substantially across an entire width of said first semiconductor die.

23. The stacked semiconductor die assembly of claim 1, further comprising at least one wire bond extending from said at least one electrical contact.

24. The stacked semiconductor die assembly of claim 23, wherein said at least one adhesive flow control dam is further configured to prevent solder flow onto at least a portion of said second semiconductor die or an extension thereof during wire bonding of said at least one electrical contact.

4. The stacked semiconductor die assembly of 1, further comprising a mounting adhesive disposed on at least a portion of a region of said upper surface of said first semiconductor die, at least a portion of said mounting adhesive disposed between said at least one adhesive flow control dam and said second semiconductor die.

5. The stacked semiconductor die assembly of claim 4, wherein said mounting adhesive is configured to be thermally conductive having an exposed surface area being heat dissipative.

6. The stacked semiconductor die assembly of claim 5, wherein said mounting adhesive comprises an Ag-filled polymer.

7. The stacked semiconductor die assembly of claim 4, wherein said mounting adhesive is configured to have a coefficient of thermal expansion selected from a group consisting of a coefficient of thermal expansion of said first semiconductor die, a coefficient of thermal expansion of said second semiconductor die, and an average of the coefficients of thermal expansion of said first semiconductor die and said second semiconductor die.

25. A stacked semiconductor die assembly comprising:

a first semiconductor die having an upper surface including at least one electrical contract, at least one region for mounting a second semiconductor die, and at least one adhesive flow control dam for preventing flow of an adhesive onto said at least one electrical contact during mounting of a second semiconductor die, said at least one adhesive flow control dam positioned between said at least one region for mounting a second semiconductor die and said at least one electrical contact; and

a second semiconductor die, said second semiconductor die adhesively mounted onto said at least one region for mounting a second semiconductor die of said first semiconductor die.

26. The stacked semiconductor die assembly of claim 25, further comprising an encapsulant surrounding at least a portion of a surface area of said first semiconductor die and said second semiconductor die.

27. The stacked semiconductor die assembly of claim 25, further comprising a carrier substrate, said first semiconductor die being disposed on said carrier substrate.

32. The stacked semiconductor die assembly of claim 25, wherein said at least one adhesive flow control dam comprises at least one decoupling capacitor coupon.

33. The stacked semiconductor die assembly of claim 32, wherein an adhesive used to mount said second semiconductor die includes an electrically insulating adhesive.

34. The stacked semiconductor die assembly of claim 25, wherein said at least one adhesive flow control dam comprises a material selected from a group consisting of polyimides, polyamides, and epoxies.

35. The stacked semiconductor die assembly of claim 25, wherein said at least one adhesive flow control dam includes a flow control dam more viscous than an adhesive used to adhesively mount said second semiconductor die.

36. The stacked semiconductor die assembly of claim 25, wherein said first semiconductor die is larger than said second semiconductor die.

37. The stacked semiconductor die assembly of claim 25, wherein said first semiconductor die is substantially the same size as said second semiconductor die.

38. The stacked semiconductor die assembly of claim 25, wherein said first semiconductor die comprises an integrated circuit semiconductor die.

39. The stacked semiconductor die assembly of claim 25, wherein said second semiconductor die comprises an integrated circuit semiconductor die.

40. The stacked semiconductor die assembly of claim 38, wherein said integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.

41. The stacked semiconductor die assembly of claim 39, wherein said integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.

42. The stacked semiconductor die assembly of claim 25, wherein said first semiconductor die comprises an interposer.

43. The stacked semiconductor die assembly of claim 25, wherein said second semiconductor die is mounted in an offset fashion relative to said first semiconductor die.

44. The stacked semiconductor die assembly of claim 25, wherein at least a portion of said second semiconductor die is in contact with said at least one adhesive flow control dam.

45. The stacked semiconductor die assembly of claim 44, wherein said at least one adhesive flow control dam is configured to deform upon said contact with said second semiconductor die.

46. The stacked semiconductor die assembly of claim 25, wherein said at least one adhesive flow control dam extends substantially across an entire width of said first semiconductor die.

47. The stacked semiconductor die assembly of claim 25, further comprising at least one wire bond extending from said at least one electrical contact.

48. The stacked semiconductor die assembly of claim 46, wherein said at least one adhesive flow control dam is further configured to prevent solder flow onto at least a portion of said second semiconductor die or an extension thereof during wire bonding of said at least one electrical contact.

28. The stacked semiconductor die assembly of 25, further comprising a mounting adhesive disposed on at least a portion of a region of said upper surface of said first semiconductor die, at least a portion of said mounting adhesive disposed between said at least one adhesive flow control dam and said second semiconductor die.

29. The stacked semiconductor die assembly of claim 28, wherein said mounting adhesive is configured to be thermally conductive having an exposed surface area being heat dissipative.

30. The stacked semiconductor die assembly of claim 29, wherein said mounting adhesive comprises an Ag-filled polymer.

31. The stacked semiconductor die assembly of claim 28, wherein said mounting adhesive is configured to have a coefficient of thermal expansion selected from a group consisting of a coefficient of thermal expansion of said first semiconductor die, a coefficient of thermal expansion of said second semiconductor die, and an average of the coefficients of thermal expansion of said first semiconductor die and said second semiconductor die.