Flip chip interconnection structure

• US 20040212098A1
• Filed: 05/20/2004
• Published: 10/28/2004
• Est. Priority Date: 03/10/2000
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Chippac Company Limited
• Inventors: Pendse, Rajendra D.
• Granted Patent: US 7,033,859 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/1601 Structure
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17107 the bump connectors connecting two common bonding areas
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81194 Lateral distribution of the bump connectors
• CPC Class Codes: H01L 2224/81345 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/53242 : the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H05K 3/325 : by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor adaptations of leads inserted in holes for press-fit connections H05K3/308
• CPC Class Codes: Y10T 428/24917 : including metal layer

Abstract

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Claims

1. A method for forming a flip chip interconnection structure, comprising

providing a first member on an IC chip and a second member on a substrate, the first member comprising a deformable material having a low yield strength and a high elongation to failure and the second member having surface asperities on a surface on a part of the second member to be bonded with the first member;

and

bringing the first member into contact with the surface on the second member and pressing the first and second members against one another using a force sufficient to cause plastic flow of part of the first member into the surface asperities on the second member.

2. The method of claim 1 wherein the first member is a bump formed on the IC chip.

3. The method of claim 1 wherein the deformable material of the first member comprises gold.

4. The method of claim 1 wherein the second member is a surface pad.

5. The method of claim 1 wherein the second member is a lead.

6. The method of claim 1 wherein the second member is a via opening.

7. The method of claim 1 wherein the second member has a plated finish.

8. The method of claim 1, said bump comprising one of a set of such bumps.

9. A flip chip interconnection structure made by the method of claim 1.

18. The method of claim 1 wherein a width of the second member surface is smaller than a width of the first member.

19. The method of claim 1 wherein the part of the second member to be bonded with the first member has a generally trapezoidal shape in transverse sectional view, the second surface comprising a plateau having a width smaller than a width of the first member.

20. The method of claim 1, further comprising, prior to pressing the first and second members against one another, dispensing a curable adhesive onto a mating surface of the substrate.

21. The method of claim 1, further comprising, prior to pressing the first and second members against one another, dispensing a curable adhesive onto a mating surface of the IC chip.

10-17. -17. (canceled)

22. A method for forming a flip chip interconnection structure, comprising

providing a first member on an IC chip and a second member on a substrate, the first member comprising a deformable material having a low yield strength and a high elongation to failure and the second member having a surface adjacent an edge on a part of the second member to be bonded with the first member;

and

bringing the first member into contact with the second member surface and pressing the first and second members against one another using a force sufficient to cause plastic flow of part of the first member around the edge.

23. The method of claim 22 wherein the first member is a bump formed on the IC chip.

24. The method of claim 22 wherein the deformable material of the first member comprises gold.

25. The method of claim 22 wherein the second member is a surface pad.

26. The method of claim 22 wherein the second member is a lead.

27. The method of claim 22 wherein the second member is a via opening, a margin of the via opening comprising the edge.

28. The method of claim 22 wherein the second member has a plated finish.

29. The method of claim 22, said bump comprising one of a set of such bumps.

30. A flip chip interconnection structure made by the method of claim 22.

31. The method of claim 22 wherein a width of the second member surface is smaller than a width of the first member.

32. The method of claim 22 wherein the part of the second member to be bonded with the first member has a generally trapezoidal shape in transverse sectional view, the second member surface comprising a plateau having a width smaller than a width of the first member.

33. The method of claim 22, further comprising, prior to pressing the first and second members against one another, dispensing a curable adhesive onto a mating surface of the substrate.

34. The method of claim 22, further comprising, prior to pressing the first and second members against one another, dispensing a curable adhesive onto a mating surface of the IC chip.

35. The method of claim 22, the second member being provided with asperities on a surface thereof.