Low dropout monolithic linear regulator having wide operating load range

• US 20040212429A1
• Filed: 04/23/2003
• Published: 10/28/2004
• Est. Priority Date: 04/23/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gupta, Vishal I., Raha, Prasun, Rincon-Mora, Gabriel A.
• Granted Patent: US 6,847,260 B2
• Time in Patent Office: Days
• US Class Current: 330/257
• CPC Class Codes: H03F 1/086 with FET's

Abstract

A monolithic low dropout regulator includes an active capacitor multiplier that is used to form the dominant pole of the regulator, thereby yielding stability. This decouples the system stability from the high-frequency power supply rejection ratio (PSRR). The PSRR at high frequencies is tuned independently using a reasonable on-chip capacitor C2.

Claims

1. A circuit comprising:

an operational amplifier;

an output pass transistor having a control node coupled to an output of the operational amplifier;

a bias transistor coupled to the output pass transistor;

a mirror transistor coupled to a control node of the bias transistor; and

a first capacitor coupled between the bias transistor and the mirror transistor such that an active capacitor multiplier is formed.

2. The circuit of claim 1 further comprising a follower circuit coupled between the operational amplifier and the output pass transistor.

3. The circuit of claim 1 further comprising a second capacitor coupled between the output pass transistor and a common node.

4. The circuit of claim 1 wherein a first input of the operational amplifier is coupled to the output pass transistor.

5. The circuit of claim 4 wherein a second input of the operational amplifier is coupled to a reference voltage node.

6. The circuit of claim 1 further comprising a current source transistor coupled to the mirror transistor.

7. The circuit of claim 6 further comprising a bias circuit coupled to the operational amplifier and to the current source transistor.

8. The circuit of claim 1 wherein the bias transistor has a width-to-length ratio larger than the mirror transistor.

9. A circuit comprising:

a differential amplifier having a first input coupled to an output node;

an output pass device coupled to the output node and having a control node coupled to an output of the differential amplifier;

a bias transistor coupled to the output node;

a mirror transistor coupled to the control node of the bias transistor, wherein the bias transistor has a width-to-length ratio larger than the mirror transistor; and

a first capacitor coupled between the output node and the mirror transistor.

10. The circuit of claim 9 further comprising a follower circuit coupled between the differential amplifier and the output pass device.

11. The circuit of claim 9 further comprising a second capacitor coupled between the output pass device and a common node.

12. The circuit of claim 9 wherein the output pass device is a transistor.

13. The circuit of claim 9 wherein a second input of the differential amplifier is coupled to a reference voltage node.

14. The circuit of claim 9 further comprising a current source transistor coupled to the mirror transistor.

15. The circuit of claim 14 further comprising a bias circuit coupled to the operational amplifier and to the current source transistor.