Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode
First Claim
1. A system for selecting between first and second arrays of memory cells each of which includes a set of row lines, the system comprising:
- a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode;
a row decoder coupled to receive a row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;
a column decoder coupled to receive a column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and
a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being coupled to receive the mode select signal and an array select signal, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.
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Accused Products
Abstract
A memory device includes 4 memory banks each of which includes first and second arrays of memory cells. A mode register is programmed with a bit that selects a high-power, large-page operating mode or a low-power, small-page operating mode. In the high-power mode, a row decoder is coupled to the row lines in both the first and second arrays. In the low-power mode, the row decoder is coupled to the row lines in only one of the arrays as determined by the state of an array select signal. The array select signal corresponds to the most significant bit of the column address, but it is applied to the memory device at the time the row address is applied to the memory device. Sense amplifiers coupled to the first and second arrays may also be selectively enabled when the row lines for the corresponding array are coupled to the row decoder.
60 Citations
2 Claims
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1. A system for selecting between first and second arrays of memory cells each of which includes a set of row lines, the system comprising:
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a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode;
a row decoder coupled to receive a row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;
a column decoder coupled to receive a column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and
a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being coupled to receive the mode select signal and an array select signal, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.
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2-69. -69 (canceled)
Specification