Hybrid MRAM array structure and operation
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Accused Products
Abstract
This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
35 Citations
48 Claims
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1-32. -32. (canceled)
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33. A method of fabricating a memory device, comprising:
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providing a substrate;
forming an access transistor on said substrate, said access transistor having a first active area and a second active area;
providing a bit line in electrical contact with said access transistor at said first active area;
providing an interconnect in electrical contact with said access transistor at said second active area;
forming a first sense line associated with said first plurality of memory bits, said first sense line being formed over said access transistor and in electrical contact with said interconnect;
forming a first plurality of memory bits, each of said first plurality of memory bits being formed over, and in electrical contact with, said first sense line;
forming a second sense line, said second sense line being formed over said first plurality of memory bits and in electrical contact with said interconnect;
forming a second plurality of memory bits, each of said second plurality of memory bits being formed over, and in electrical contact with, said second sense line. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. A method for forming a memory device, comprising:
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providing a sense amplifier;
providing an interconnect;
providing an access transistor, said access transistor being capable of electrically connecting said sense amplifier with said interconnect;
providing a plurality of array planes over said access transistor, each of said array planes comprising a plurality of memory cells organized into a plurality of rows and a plurality of columns, each of said plurality of columns being associated with a respective common line; and
providing a plurality of array planes over said access transistor, each of said array planes comprising a plurality of memory cells organized into a plurality of rows and a plurality of columns;
providing a plurality of common lines, each of said common lines being associated with and coupled to a respective column of said plurality of memory cells; and
providing a plurality of sense lines, each of said sense lines being associated with and coupled to a respective row of said plurality of memory cells. - View Dependent Claims (46, 47, 48)
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Specification