Process and device for generating pulses for the transmission of a pulsed signal of the ultra wideband type

• US 20040213325A1
• Filed: 03/05/2004
• Published: 10/28/2004
• Est. Priority Date: 03/06/2003
• Status: Active Grant

• Current Assignee: STMicroelectronics NV
• Original Assignee: STMicroelectronics NV
• Inventors: Smaini, Lydi, Helal, Didier
• Granted Patent: US 7,321,608 B2
• Time in Patent Office: Days
• US Class Current: 375/130
• CPC Class Codes: H04B 1/7174 Pulse generation in general H04L25/03834
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation

Abstract

Successive groups of N bits are delivered at a delivery frequency Fe greater than a predetermined frequency PRF. At least one of the successive groups includes at least one subgroup of at least one bit defining at least one digital cue of position and of shape of at least one base pulse within a window of length 1/PRF. This digital cue is converted into the base pulse, and the base pulse is filtered using a high-pass filter for providing a pulse of the ultra wideband type within the window with a temporal accuracy equal to 1/N*Fe.

Claims

1-38. -38 (Cancelled).

39. A process for generating pulses for transmitting a pulsed signal of an ultra wideband type, the process comprising:

generating successive groups of N bits at a frequency Fe greater than a predetermined frequency PRF, at least one of the successive groups comprising at least one subgroup of at least one bit defining at least one digital cue of position and of shape of at least one base pulse within a window of length 1/PRF;

converting the at least one digital cue of position and of shape into the at least one base pulse; and

filtering the at least one base pulse using at least one high-pass filter for providing a filtered pulse of the ultra wideband type positioned within the window with a temporal accuracy equal to 1/N*Fe.

40. A process according to claim 39, further comprising selecting a cutoff frequency of the at least one high-pass filter so that the filtered pulse has a power spectrum in a frequency domain whose bandwidth at −

10 dB is greater than 500 MHz.

41. A process according to claim 39, further comprising selecting a cutoff frequency of the at least one high-pass filter so that the filtered pulse has a power spectrum in a frequency domain whose bandwidth at −

10 dB is greater than 20% of a center frequency.

42. A process according to claim 39, wherein a cutoff frequency of the at least one high-pass filter is about 3 GHz.

43. A process according to claim 39, wherein the at least one base pulse comprises at least four transitions.

44. A process according to claim 43, wherein the at least one base pulse comprises a succession of identical pulses.

45. A process according to claim 43, wherein the at least one high-pass filter comprises at least one bandpass filter configured so that only the power frequency spectrum of the at least one base pulse centered around a fundamental frequency is passed.

46. A process according to claim 45, wherein the at least one bandpass filter has a low cutoff frequency of about 3 GHz and a high cutoff frequency of about 10 GHz.

47. A process according to claim 39, wherein the converting is performed using a converter comprising a combinatorial logic unit.

48. A process according to claim 47, wherein the combinatorial logic unit comprises a plurality of EXCLUSIVE OR logic gates connected together in a tree-like arrangement.

49. A process according to claim 47, wherein the converter comprises at least one delay element associated with the combinatorial logic unit.

50. A process according to claim 47, wherein the generating is performed using a processor;

and wherein the converter comprises;

a programmable clock circuit receiving a base clock signal having the frequency Fe, and providing N clock signals all having a same frequency Fe but being mutually shifted by 1/N*Fe; and

N flip-flops having inputs connected to the processor, the N flip-flops being respectively commanded by the N clock signals, and respectively delivering N output signals to the combinatorial logic unit.

51. A process according to claim 50, wherein the converter comprises a differential structure downstream from the N flip-flops;

and wherein the at least one high-pass filter also comprises a differential structure.

52. A process according to claim 39, wherein the at least one subgroup of at least one bit comprises a plurality of bits, with a first bit of the at least one subgroup defining a position of the at least one base pulse within the window, and an entire set of the plurality bits of the at least one subgroup defining a shape of the at least one base pulse.

53. A process according to claim 39, wherein at least two of the successive groups include the at least one subgroup of at least one bit respectively defining at least two digital cues of position and of shape of at least two pulses within the window.

54. A process according to claim 39, wherein the at least one group comprises a plurality of subgroups of bits respectively defining a plurality of digital cues of position and of shape of a plurality of pulses within the window.

55. A process according to claim 39, wherein the temporal accuracy is equal to or less than 100 picoseconds.

56. A process according to claim 55, wherein N is a power of two, and the frequency of delivery is about a few hundred MHz, and the temporal accuracy is equal to or less than 50 picoseconds.

57. A device for generating pulses for transmitting a pulsed signal of an ultra wideband type, the device comprising:

a processor for generating successive groups of N bits at a frequency Fe greater than a predetermined frequency PRF, at least one of the successive groups comprising at least one subgroup of at least one bit defining at least one digital cue of position and of shape of at least one base pulse within a window of length 1/PRF;

a converter for converting the at least one digital cue of position and of shape into the at least one base pulse; and

at least one high-pass filter connected to an output of said converter, and providing a filtered pulse of the ultra wideband type positioned within the window with a temporal accuracy equal to 1/N*Fe.

58. A device according to claim 57, wherein a cutoff frequency of said at least one high-pass filter has a power spectrum in a frequency domain whose bandwidth at −

10 dB is greater than 500 MHz.

59. A device according to claim 57, wherein a cutoff frequency of said at least one high-pass filter has a power spectrum in a frequency domain whose bandwidth at −

10 dB is greater than 20% of a center frequency.

60. A device according to claim 57, wherein a cutoff frequency of said at least one high-pass filter is about 3 GHz.

61. A device according to claim 57, wherein the at least one base pulse comprises at least four transitions.

62. A device according to claim 61, wherein the at least one base pulse comprises a succession of identical pulses.

63. A device according to claims 61, wherein said at least one high-pass filter comprises at least one bandpass filter configured so that only the power frequency spectrum of the at least one base pulse centered around a fundamental frequency is passed.

64. A device according to claim 63, wherein said at least one bandpass filter has a low cutoff frequency of about 3 GHz and a high cutoff frequency of about 10 GHz.

65. A device according to claim 57, wherein said converter comprises a combinatorial logic unit.

66. A device according to claim 65, wherein said combinatorial logic unit comprises a plurality of EXCLUSIVE OR logic gates connected together in a tree-like configuration.

67. A device according to claim 65, wherein said converter comprises at least one delay element associated with said combinatorial logic unit.

68. A device according to claim 65, wherein said converter comprise:

a programmable clock circuit receiving a base clock signal having the frequency Fe, and providing N clock signals all having a same frequency Fe but being mutually shifted by 1/N*Fe; and

N flip-flops having inputs connected to said processor, said N flip-flops being respectively commanded by the N clock signals, and respectively delivering N output signals to said combinatorial logic unit.

69. A device according to claim 68, wherein said converter comprises a differential structure downstream from said N flip-flops;

and wherein said at least one high-pass filter also comprises a differential structure.

70. A device according to one of claim 57, wherein the at least one subgroup of at least one bit comprises a plurality of bits, with a first bit of the at least one subgroup defining a position of the at least one base pulse within the window, and an entire set of the plurality bits of the at least one subgroup defining a shape of the at least one base pulse.

71. A device according to claim 57, wherein at least two of the successive groups include the at least one subgroup of at least one bit respectively defining at least two digital cues of position and of shape of at least two pulses within the window.

72. A device according to claim 57, wherein the at least one group comprises a plurality of subgroups of bits respectively defining a plurality of digital cues of position and of shape of a plurality of pulses within the window.

73. A device according to claim 57, wherein the temporal accuracy is equal to or less than 100 picoseconds.

74. A device according to claim 73, wherein N is a power of two, and the frequency of delivery is about a few hundred MHz, and the temporal accuracy is equal to or less than 50 picoseconds.

75. A device according to claim 57, wherein said converter comprises a CMOS converter.

76. A terminal of a wireless transmission system comprising:

a pulse generator device comprising

a processor for generating successive groups of N bits at a frequency Fe greater than a predetermined frequency PRF, at least one of the successive groups comprising at least one subgroup of at least one bit defining at least one digital cue of position and of shape of at least one base pulse within a window of length 1/PRF,

a converter for converting the at least one digital cue of position and of shape into the at least one base pulse, and

at least one high-pass filter connected to an output of said converter, and providing a filtered pulse of an ultra wideband type positioned within the window with a temporal accuracy equal to 1/N*Fe; and

a power amplifier connected to an output of said pulse generator device for amplifying the filtered pulse.

77. A terminal according to claim 76, wherein a cutoff frequency of said at least one high-pass filter has a power spectrum in a frequency domain whose bandwidth at −

10 dB is greater than 500 MHz.

78. A terminal according to claim 76, wherein a cutoff frequency of said at least one high-pass filter has a power spectrum in a frequency domain whose bandwidth at −

10 dB is greater than 20% of a center frequency.

79. A terminal according to claim 76, wherein a cutoff frequency of said at least one high-pass filter is about 3 GHz.

80. A terminal according to claim 76, wherein the at least one base pulse comprises at least four transitions.

81. A terminal according to claim 80, wherein the at least one base pulse comprises a succession of identical pulses.

82. A terminal according to claims 80, wherein said at least one high-pass filter comprises at least one bandpass filter configured so that only the power frequency spectrum of the at least one base pulse centered around a fundamental frequency is passed.

83. A terminal according to claim 82, wherein said at least one bandpass filter has a low cutoff frequency of about 3 GHz and a high cutoff frequency of about 10 GHz.

84. A terminal according to claim 76, wherein said converter comprises a combinatorial logic unit.

85. A terminal according to claim 84, wherein said combinatorial logic unit comprises a plurality of EXCLUSIVE OR logic gates connected together in a tree-like configuration.

86. A terminal according to claim 84, wherein said converter comprises at least one delay element associated with said combinatorial logic unit.

87. A terminal according to claim 84, wherein said converter comprise:

a programmable clock circuit receiving a base clock signal having the frequency Fe, and providing N clock signals all having a same frequency Fe but being mutually shifted by 1/N*Fe; and

N flip-flops having inputs connected to said processor, said N flip-flops being respectively commanded by the N clock signals, and respectively delivering N output signals to said combinatorial logic unit.

88. A terminal according to claim 87, wherein said converter comprises a differential structure downstream from said N flip-flops;

and wherein said at least one high- pass filter also comprises a differential structure.

89. A terminal according to one of claim 76, wherein the at least one subgroup of at least one bit comprises a plurality of bits, with a first bit of the at least one subgroup defining a position of the at least one base pulse within the window, and an entire set of the plurality bits of the at least one subgroup defining a shape of the at least one base pulse.

90. A terminal according to claim 76, wherein at least two of the successive groups include the at least one subgroup of at least one bit respectively defining at least two digital cues of position and of shape of at least two pulses within the window.

91. A terminal according to claim 76, wherein the at least one group comprises a plurality of subgroups of bits respectively defining a plurality of digital cues of position and of shape of a plurality of pulses within the window.

92. A terminal according to claim 76, wherein the temporal accuracy is equal to or less than 100 picoseconds.

93. A terminal according to claim 92, wherein N is a power of two, and the frequency of delivery is about a few hundred MHz, and the temporal accuracy is equal to or less than 50 picoseconds.

94. A terminal according to claim 76, wherein said converter comprises a CMOS converter.