Method for fabricating image sensor semiconductor package

• US 20040214372A1
• Filed: 05/17/2004
• Published: 10/28/2004
• Est. Priority Date: 04/07/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Walter Moden
• Inventors: Moden, Walter
• Granted Patent: US 6,969,632 B2
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48744 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48747 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/83951 Forming additional members, e.g. for reinforcing, fillet sealant
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 24/31 Structure, shape, material or disposition of the layer connectors after the connecting process
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/50 : Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/86 : using tape automated bonding [TAB]
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate

Abstract

A semiconductor package includes a substrate, and a semiconductor die flip chip mounted to the substrate. The package also includes substrate circuitry on a circuit side of the substrate, die circuitry on a back side of the die, terminal contacts on the die circuitry, bonded connections between the substrate circuitry and the die circuitry, and an encapsulant on the bonded connections and edges of the die. The die can include an image sensor on the circuit side configured to receive electromagnetic radiation transmitted through the substrate. A method for fabricating the package includes the step of providing a wafer with multiple dice, forming the die circuitry on the dice, and singulating the wafer into individual dice. The method also includes the steps of providing a substrate panel with multiple substrates, forming the substrate circuitry on the substrates, flip chip bonding the dice to the substrates, forming bonded connections between the dice and the substrates, forming the terminal contacts on the die circuitry, and singulating the panel into separate components.

Claims

1-40. -40. (canceled)

41. A method for fabricating a semiconductor package comprising:

providing a semiconductor die comprising a die circuitry on a back side thereof comprising a plurality of terminal contacts;

providing a substrate comprising a substrate circuitry;

flip chip bonding the die to the substrate circuitry;

wire bonding wires between the die circuitry and the substrate circuitry.

42. The method of claim 41 further comprising encapsulating the wires and peripheral edges of the die.

43. The method of claim 41 wherein the substrate comprises a transparent material and the die includes an active area configured to receive electromagnetic radiation transmitted through the substrate.

44. The method of claim 41 wherein the terminal contacts comprise bumps or balls in a grid array.

45. A method for fabricating a semiconductor package comprising:

providing a semiconductor die having a circuit side, a back side and peripheral edges;

forming a die circuitry on the back side comprising a plurality of terminal contacts;

providing a transparent substrate;

forming a substrate circuitry on the substrate;

flip chip bonding the die to the substrate with the circuit side thereof facing the substrate;

bonding wires to the die circuitry and to the substrate circuitry; and

forming an encapsulant on the wires and on the peripheral edges.

46. The method of claim 45 wherein the forming the die circuitry comprises forming die bonding contacts on the back side for bonding the wires.

47. The method of claim 45 wherein the forming the substrate circuitry comprising forming substrate bonding contacts on the substrate for bonding the wires.

48. The method of claim 45 wherein the die includes an active area configured to receive electromagnetic radiation transmitted through the substrate.

49. The method of claim 45 wherein the die includes an image sensor.

50. The method of claim 45 wherein the forming the die circuitry step is performed on a wafer containing a plurality of dice.

51. The method of claim 45 wherein the forming the substrate circuitry step is performed on a panel containing a plurality of substrates.

52. A method for fabricating a semiconductor package comprising:

providing a semiconductor die having peripheral edges, a circuit side, a back side and a plurality of die contacts on the circuit side;

forming a plurality of die bonding contacts on the back side and a plurality terminal contacts on the back side in electrical communication with the die bonding contacts;

providing a substrate comprising a plurality of substrate contacts and a plurality of substrate bonding contacts;

bonding the die contacts to the substrate contacts;

forming bonded connections between the die bonding contacts and the substrate bonding contacts; and

forming an encapsulant on the bonded connections and on the peripheral edges of the die.

53. The method of claim 52 wherein the substrate comprises a transparent material and the die includes an active area on the circuit side configured to receive electromagnetic radiation transmitted through the substrate.

54. The method of claim 52 wherein the bonded connections comprise wire bonded wires.

55. The method of claim 52 wherein the bonded connections comprised TAB bonded tape leads.

56. The method of claim 52 wherein the substrate, the encapsulant and the package have a same peripheral outline.

57. A method for fabricating a semiconductor package comprising:

providing a semiconductor die having a circuit side, a back side and peripheral edges;

attaching a tape decal die circuitry to the back side comprising a plurality of terminal leads;

providing a transparent substrate;

forming a substrate circuitry on the substrate;

flip chip bonding the die to the substrate with the circuit side thereof facing the substrate;

bonding the tape leads to the substrate circuitry; and

forming an encapsulant on the tape leads and on the peripheral edges.

58. The method of claim 57 wherein the die includes an active area configured to receive electromagnetic radiation transmitted through the substrate.

59. The method of claim 57 wherein the die includes an image sensor.

60. The method of claim 57 wherein the attaching the tape decal die circuitry step is performed on a wafer containing a plurality of dice.

61. The method of claim 57 wherein the forming the substrate circuitry step is performed on a panel containing a plurality of substrates.

62. A method for fabricating a semiconductor package comprising:

providing a semiconductor die having an active area and bumped die contacts on a circuit side thereof in electrical communication with the active area;

forming a die circuitry on a back side of the die comprising terminal contacts and die bonding contacts in electrical communication with the terminal contacts;

providing a transparent substrate;

forming a substrate circuitry on the substrate comprising substrate contacts and substrate bonding contacts in electrical communication with the substrate contacts;

mounting the die to the substrate by bonding the bumped die contacts to the substrate contacts with the active area positioned to receive electromagnetic radiation transmitted through the substrate; and

bonding wires or leads to the die bonding contacts and to the substrate bonding contacts.

63. The method of claim 62 wherein the forming the die circuitry step comprises depositing or patterning a metal layer.

64. The method of claim 62 further comprising forming an encapsulant on the wires or the leads configured to seal the die on the substrate.

65. The method of claim 62 wherein the forming the die circuitry step comprises attaching a tape decal to the back side.

66. The method of claim 62 wherein the substrate comprises a glass plate having opposing peripheral edges and the substrate bonding contacts are located proximate to the peripheral edges.

67. The method of claim 62 wherein the die bonding contacts are located proximate to opposing peripheral edges of the die.

68-73. -73. (canceled)