Antenna switches including field effect transistors

• US 20040214530A1
• Filed: 04/25/2003
• Published: 10/28/2004
• Est. Priority Date: 04/25/2003
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Andersson, Jesper, Brandt, Per-Olof
• Granted Patent: US 7,197,284 B2
• Time in Patent Office: Days
• US Class Current: 455/90.1
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

The present invention provides a transceiver circuit that includes a transmission amplifier coupled with an antenna input/output node. The transmission amplifier is configured to amplify communications to be transmitted from the transceiver circuit. The transceiver circuit further includes a receiver and a field effect transistor. The receiver includes a receiver input coupled with the antenna input/output node. The field effect transistor is coupled between the receiver input and an electrical reference. The field effect transistor is configured to provide an open circuit when communications are received at the receiver input and to provide a closed circuit when communications are not being received at the receiver input.

Claims

1. A transceiver circuit comprising:

a transmission amplifier coupled with an antenna input/output node wherein the transmission amplifier is configured to amplify communications to be transmitted from the transceiver circuit;

a receiver including a receiver input coupled with the antenna input/output node; and

a field effect transistor coupled between the receiver input and an electrical reference wherein the field effect transistor is configured to provide an open circuit when receiving communications at the receiver input and wherein the field effect transistor is configured to provide a closed circuit when not receiving communications at the receiver input.

2. A transceiver circuit according to claim 1 wherein the transmission amplifier and the field effect transistor are integrated on a same semiconductor chip.

3. A transceiver circuit according to claim 1 wherein the transceiver circuit is integrated in a communications device.

4. A transceiver circuit according to claim 1 further comprising:

an isolation device coupled between the transmission amplifier and the antenna input/output node and between the transmission amplifier and the receive port input.

5. A transceiver circuit according to claim 4 further comprising:

a bias circuit coupled with the antenna input/output node wherein the bias circuit is configured to provide a low impedance at the isolation device when transmitting communications from the transmission amplifier and to provide a high impedance at the isolation device when communications are not being transmitted from the transmission amplifier.

6. A transceiver circuit according to claim 5 wherein the isolation device comprises a PIN diode.

7. A transceiver circuit according to claim 6 wherein the bias circuit comprises resistive coupling of the transmission amplifier output to a source voltage and a switch configured to couple the antenna input/output node to ground when transmitting communications from the transmission amplifier and configured to decouple the antenna input/output node from ground when not transmitting communications from the transmission amplifier.

8. A transceiver circuit according to claim 6 wherein the bias circuit comprises a resistive coupling of the transmission amplifier output to ground and a switch configured to couple the antenna input/output node to a supply voltage when transmitting communications from the transmission amplifier and configured to decouple the antenna input/output node from the supply voltage when not transmitting communications from the transmission amplifier.

9. A transceiver circuit according to claim 1 further comprising:

a resistive element coupled to a gate of the field effect transistor wherein the field effect transistor is responsive to an input signal applied through the resistive element coupled to the gate thereof.

10. A transceiver circuit according to claim 1 further comprising:

a transmission line coupled between the receiver input and the antenna input/output node.

11. A transceiver circuit according to claim 10 further comprising:

a capacitor coupled between the receiver input and an electrical reference.

13. A transceiver circuit according to claim 1 wherein a channel region of the field effect transistor is coupled to ground through a backside of the substrate.

14. A transceiver circuit according to claim 1 further comprising:

a second receiver including a second receiver input coupled with the antenna input/output node; and

a second field effect transistor coupled between the second receiver input and the electrical reference wherein the second field effect transistor is configured to provide an open circuit when receiving communications at the second receiver input and wherein the field effect transistor is configured to provide a closed circuit when not receiving communications at the second receiver input.

15. A transceiver circuit according to claim 14 wherein the first and second field effect transistors are further configured to provide the closed circuit when transmitting communications from the transmission amplifier.

16. A transceiver circuit according to claim 1 further comprising:

a second transmission amplifier coupled with a second antenna input/output node wherein the second transmission amplifier is configured to amplify communications to be transmitted from the transceiver circuit;

a frequency selection circuit coupled between the first and second antenna input/output nodes wherein the frequency selection circuit is configured to couple frequencies in a first frequency band to/from the first antenna input/output node and to couple frequencies in a second frequency band to/from the second antenna input/output node;

a second receiver including a receiver input coupled with the antenna input/output node; and

a second field effect transistor coupled between the second receiver input and the electrical reference wherein the second field effect transistor is configured to provide an open circuit when receiving communications at the second receiver input and wherein the second field effect transistor is configured to provide a closed circuit when not receiving communications at the second receiver input.

12. A transceiver circuit according to claim 111 wherein the capacitor has a capacitance that is approximately equal to a drain to source capacitance of the field effect transistor.

17. A transceiver circuit comprising:

a transmission amplifier coupled with an antenna input/output node wherein the transmission amplifier is configured to amplify communications to be transmitted from the transceiver circuit;

a receiver including a receiver input coupled with the antenna input/output node;

an isolation device coupled between the transmission amplifier and the antenna input/output node and between the transmission amplifier and the receiver input;

a bias circuit coupled with the antenna input/output node wherein the bias circuit is configured to provide a low impedance at the isolation device when transmitting communications from the transmission amplifier and to provide a high impedance at the isolation device when communications are not being transmitted from the transmission amplifier.

18. A transceiver circuit according to claim 17 wherein the isolation device comprises a PIN diode.

19. A transceiver circuit according to claim 18 wherein the bias circuit comprises a resistive coupling of the transmission amplifier output to a source voltage and a switch configured to couple the antenna input/output node to ground when transmitting communications from the transmission amplifier and configured to decouple the antenna input/output node from ground when not transmitting communications from the transmission amplifier.

20. A transceiver circuit according to claim 19 wherein the switch is further configured to decouple the antenna input/output node from ground when receiving communications at the receiver.

21. A transceiver circuit according to claim 18 wherein the bias circuit comprises a resistive coupling of the transmission amplifier output to ground and a switch configured to couple the antenna input/output node to a supply voltage when transmitting communications from the transmission amplifier and configured to decouple the antenna input/output node from the supply voltage when not transmitting communications from the transmission amplifier.

22. A transceiver circuit according to claim 21 wherein the switch is further configured to decouple the antenna input/output node from a supply voltage when receiving communications at the receiver.

23. A transceiver circuit according to claim 17 further comprising:

a field effect transistor coupled between the receiver input and an electrical reference wherein the field effect transistor is configured to provide an open circuit when receiving communications at the receiver input and wherein the field effect transistor is configured to provide a closed circuit when not receiving communications at the receiver input.

24. A transceiver circuit according to claim 23 wherein the transmission amplifier and the field effect transistor are integrated on a same semiconductor chip.

25. A transceiver circuit according to claim 23 further comprising:

a resistive element coupled to a gate of the field effect transistor wherein the field effect transistor is responsive to an input signal applied through the resistive element coupled to the gate thereof.

26. A transceiver circuit according to claim 23 further comprising:

a transmission line coupled between the receiver input and the antenna input/output node.

27. A transceiver circuit according to claim 23 further comprising:

a capacitor coupled between the receiver input and an electrical reference.

28. A transceiver circuit according to claim 27 wherein the capacitor has a capacitance that is approximately equal to a drain to source capacitance of the field effect transistor.

29. A transceiver circuit according to claim 23 wherein a channel region of the field effect transistor is coupled to ground through a backside of the substrate.

30. A transceiver circuit according to claim 17 further comprising:

a second receiver including a second receiver input coupled with the antenna input/output node; and

a second bias circuit coupled with the antenna input/output node wherein the second bias circuit is configured to provide a low impedance at the isolation device when transmitting communications from the transmission amplifier and to provide a high impedance at the isolation device when communications are not being transmitted from the transmission amplifier.

31. A transceiver circuit according to claim 17 further comprising:

a second transmission amplifier coupled with a second antenna input/output node wherein the second transmission amplifier is configured to amplify communications to be transmitted from the transceiver circuit;

a frequency selection circuit coupled between the first and second antenna input/output nodes wherein the frequency selection circuit is configured to couple frequencies in a first frequency band to/from the first antenna input/output node and to couple frequencies in a second frequency band to/from the second antenna input/output node;

a second receiver including a second receiver input coupled with the second antenna input/output node;

a second isolation device coupled between the second transmission amplifier and the second antenna input/output node and between the second transmission amplifier and the second receiver input;

a second bias circuit coupled with the second antenna input/output node wherein the second bias circuit is configured to provide a low impedance at the second isolation device when transmitting communications from the second transmission amplifier and to provide a high impedance at the second isolation device when communications are not being transmitted from the second transmission amplifier.

32. A transceiver circuit according to claim 17 wherein the transceiver circuit is integrated in a communications device.

33. A communications device comprising:

a transmission amplifier coupled with an antenna input/output node wherein the transmission amplifier is configured to amplify communications to be transmitted from the communications device;

a receiver including a receiver input coupled with the antenna input/output node; and

a field effect transistor coupled between the receiver input and an electrical reference wherein the field effect transistor is configured to provide an open circuit when receiving communications at the receiver input and wherein the field effect transistor is configured to provide a closed circuit when not receiving communications at the receiver input.

34. A communications device comprising:

a transmission amplifier coupled with an antenna input/output node wherein the transmission amplifier is configured to amplify communications to be transmitted from the communications device;

a receiver including a receiver input coupled with the antenna input/output node;

an isolation device coupled between the transmission amplifier and the antenna input/output node and between the transmission amplifier and the receiver input;

a bias circuit coupled with the antenna input/output node wherein the bias circuit is configured to provide a low impedance at the isolation device when transmitting communications from the transmission amplifier and to provide a high impedance at the isolation device when communications are not being transmitted from the transmission amplifier.