Dynamically selecting processor cores for overall power efficiency

• US 20040215987A1
• Filed: 04/25/2003
• Published: 10/28/2004
• Est. Priority Date: 04/25/2003
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Ranganathan, Parthasarathy, Farkas, Keith, Jouppi, Norman P., Mayo, Robert N.
• Granted Patent: US 7,093,147 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 9/5088 involving task migration
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system for conserving operating power includes a number of computer hardware processor cores that differ amongst themselves in at least in their respective operating power requirements and processing capabilities. A monitor gathers performance metric information from each of the computer hardware processor cores that is specific to a particular run of application software then executing. A workload transfer mechanism transfers the executing application software to a second computer hardware processor core in a search for reduced operating power. A transfer delay mechanism is connected to delay a subsequent transfer of the executing application software if the system operating power may be conserved by such delay.

Claims

1. A multi-core processor computer system for conserving average operating power, comprising:

a plurality of computer hardware processor cores that differ amongst themselves in at least in their respective operating power requirements and processing capabilities;

a monitor for gathering performance and power metric information from each of said computer hardware processor cores that is specific to a particular run of application software then executing on a first computer hardware processor core in the plurality of computer hardware processor cores; and

a workload transfer and control mechanism connected to the plurality of computer hardware processor cores and to the monitor, and providing for a transfer of said application software then executing to a second computer hardware processor core in the plurality of computer hardware processor cores.

2. The computer system of claim 1, wherein:

the workload transfer mechanism transfers depend on a search for a better power delay product.

3. The computer system of claim 1, further comprising:

a transfer delay mechanism connected to delay a subsequent transfer of said application software then executing if an overall operating power of the system may be conserved by said delay.

4. The computer system of claim 1, wherein:

the monitor for gathering performance and power information can be based on metrics derived from other similar workloads on other similar cores.

5. The computer system of claim 1, wherein:

the plurality of computer hardware processor cores comprise dissimilar processor cores all disposed on a single semiconductor die.

6. The computer system of claim 1, wherein:

the workload transfer mechanism includes a power switch providing for the independent interruption of operating power to selected individual ones of the plurality of computer hardware processor cores not then required to execute any software.

7. The computer system of claim 1, wherein:

the workload transfer mechanism provides for a skipping over of individual ones of the plurality of computer hardware processor cores to transfer to that are already executing another thread of application software.

8. The computer system of claim 1, wherein:

the workload transfer mechanism provides for input from the application or the user on the feasibility and benefits of moving workloads between the cores.

9. The computer system of claim 1, wherein:

the workload transfer mechanism can be disabled at user, operating system, or application discretion.

10. The computer system of claim 1, wherein:

workloads are statically associated for execution on specific processor cores, possibly based on earlier profiling history.

11. The computer system of claim 1, further comprising:

an operating system connected to the plurality of computer hardware processor cores, the monitor, and the workload transfer mechanism, and that provides for assessments of information received from the monitor, and that further provides for management of any transfers of an application program between individuals of the plurality of computer hardware processor cores.

12. A method for operating a multi-core processor computer system, the method comprising the steps of:

pooling at least two processor cores on a single semiconductor chip that have differing operating power requirements;

executing a software application program on one of said processor cores;

collecting a performance metric from said one of said processor cores;

comparing said performance metric to another performance metric obtained from another of said processor cores; and

transferring said software application program to execute on said another of said processor cores depending on the power consumption.

13. The method of claim 12, wherein:

the step of pooling is such that said least two processor cores differ also in their respective processor core resources.

14. The method of claim 12, wherein:

the step of pooling is such that said least two processor cores are capable of executing the same instruction sets.

15. The method of claim 12, wherein:

the step of pooling is such that the properties of said least two processor cores are determined based on at least one of common workload requirements on said cores, and any area constraints of the cores.

16. The method of claim 12, further comprising the steps of:

timing the duration of the step of executing such that the step of collecting said performance metric is substantially shorter compared to a time allowed to lapse between successive steps of collecting.

17. A method for operating a multi-core processor computer system, the method comprising the steps of:

pooling at least two processor cores on a single semiconductor chip that have differing operating power models and performance levels;

executing a software application program on a first one of said processor cores for a first time interval;

collecting a first performance metric from said first one of said processor cores;

transferring said software application program to execute on a second one of said processor cores for a second time interval that is shorter than said first time interval;

collecting a second performance metric from said second one of said processor cores;

comparing said first and second performance metrics to determine a favored one of said processor cores according to a predetermined criteria; and

transferring said software application program to execute on said second one of said processor cores depending on a result obtained in the step of comparing.

18. The method of claim 17, further comprising the step of:

looping back from the step of transferring to the step of executing to constantly search for one of said processor cores that will be then favored in the step of comparing.