Power-up of multiple processors when a voltage regulator module has failed

• US 20040215991A1
• Filed: 04/23/2003
• Published: 10/28/2004
• Est. Priority Date: 04/23/2003
• Status: Abandoned Application

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: McAfee, Martin, Vasudevan, Bharath
• Application Number:
  US10/421,277
• Publication Number:
  US 20040215991A1
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

In an information handling system, voltage regulator modules (VRM) are first enabled and determined to be operational before enabling an associated processor. If a VRM is determined not to be operational, then the associated processor is disabled. Once all VRMs are determined to be operational or not operational and the associated processors are enabled or disabled as the case may be, the information handling system is operationally started-up with all operational VRMs and associated processors functioning.

Claims

1. An information handling system having a plurality of processors and a plurality of voltage regulator modules associated therewith, said system comprising:

a plurality of processors;

a plurality of voltage regulator modules, each of said plurality of voltage regulator modules supplying operating voltages to associated ones of said plurality of processors; and

a power controller, wherein said power controller enables each of said plurality of voltage regulator modules, checks each enabled one of said plurality of voltage regulator modules for proper operation, and enables each of said plurality of processors that is associated with a properly operating one of said plurality of voltage regulator modules.

2. The information handling system according to claim 1, wherein the information handling system is selected from the group consisting of a computer system, a data storage system, a personal computer workstation, a portable computer, a computer server, a print server, a network router, a network hub, a network switch, a storage area network disk array, a RAID disk system and a telecommunications switch.

3. The information handling system according to claim 1, wherein said power controller is selected from the group consisting of a complex programmable logic device (CPLD) and an application specific integrated circuit (ASIC).

4. The information handling system according to claim 1, wherein said plurality of processors, said plurality of voltage regulator modules and said power controller are connected on a printed circuit board (PCB).

5. The information handling system according to claim 4, wherein the printed circuit board is a motherboard.

6. The information handling system according to claim 5, wherein each of said plurality of voltage regulator modules are on separate daughterboards, and each daughterboard is coupled to the motherboard.

7. The information handling system according to claim 1, wherein said plurality of processors are grouped into at least two processor nodes.

8. The information handling system according to claim 1, wherein said power controller is a plurality of power controllers, each of said plurality of power controllers is associated with corresponding ones of said plurality of voltage regulator modules and said plurality of processors.

9. The information handling system according to claim 1, wherein said power controller enables each of said plurality of voltage regulator modules and verifies that each enabled one of said plurality of voltage regulator modules returns a power good signal within a certain time limit.

10. The information handling system according to claim 9, wherein the certain time limit is about 150 milliseconds.

11. The information handling system according to claim 1, wherein said power controller initiates a power-on self test boot-up of said information handling system after enabling and checking each of said plurality of voltage regulator modules.

12. The information handling system according to claim 1, wherein said power controller disables a processor associated with a non-operating voltage regulator module.

13. The information handling system according to claim 1, wherein said power controller determines whether any of said plurality of processors are in thermal overload.

14. A method for power-up of multiple processors in an information handling system, said method comprising the steps of:

a) enabling a first voltage regulator module;

b) determining whether the enabled first voltage regulator is operational;

c) enabling a first processor if the enabled first voltage regulator is operational, otherwise disabling the first processor;

d) enabling another voltage regulator module;

e) enabling another processor if the enabled another voltage regulator is operational, otherwise disabling the another processor;

f) determining whether all voltage regulator modules have been enabled, if not then repeating steps d) through f) and if so then;

g) enabling an information handling system start-up.

15. The method according to claim 14, wherein the steps of determining whether enabled voltage regulators are operational comprises the steps of determining whether a power good signal is returned from each of the enabled voltage regulators.

16. The method according to claim 15, wherein the steps of determining whether enabled voltage regulators are operational further comprise the steps of determining whether the power good signal is returned from each of the enabled voltage regulators within a certain time limit.

17. The method according to claim 16, wherein the certain time limit is about 150 milliseconds.

18. The method according to claim 14, wherein the step of enabling an information handling system start-up comprises the step of power-on self-test (POST) of the information handling system.

19. The method according to claim 14, wherein the steps of disabling the processors comprise the steps of holding the disabled processors in reset.

20. The method according to claim 14, further comprising the steps of determining whether the processors are in thermal overload.

21. The method according to claim 20, further comprising the step of disabling the processors in thermal overload.

22. The method according to claim 21, further comprising the step of disabling voltage regulator modules that are associated with the processors in thermal overload.