Routing structure for transceiver core

• US 20040216071A1
• Filed: 04/22/2003
• Published: 10/28/2004
• Est. Priority Date: 04/22/2003
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Miller, Leah M.
• Granted Patent: US 7,062,742 B2
• Time in Patent Office: Days
• US Class Current: 716/12
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H05K 1/0219 Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/09227 Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• CPC Class Codes: H05K 2201/10674 Flip chip

Abstract

A routing structure for a transceiver core, the routing structure including a transmitter block design and a receiver block design. The transmitter block design includes two dedicated transmitter power contacts, two common ground contacts, and two transmitter signal contacts in a transmitter differential pair. The two transmitter signal contacts are both adjacent each of the two dedicated transmitter power contacts and each of the two common ground contacts. The receiver block design includes two dedicated receiver power contacts, two common ground contacts, and two receiver signal contacts in a receiver differential pair. The two receiver signal contacts are both adjacent each of the two dedicated receiver power contacts and each of the two common ground contacts.

Claims

1. A routing structure for a transceiver core, comprising:

a transmitter block design including two dedicated transmitter power contacts, two common ground contacts, and two transmitter signal contacts in a transmitter differential pair, where the two transmitter signal contacts are both adjacent each of the two dedicated transmitter power contacts and each of the two common ground contacts, and

a receiver block design including two dedicated receiver power contacts, two common ground contacts, and two receiver signal contacts in a receiver differential pair, where the two receiver signal contacts are both adjacent each of the two dedicated receiver power contacts and each of the two common ground contacts.

2. The routing structure of claim 1, wherein the transmitter block design is repeated within a platform design for as many transmitter cores as are included in an ASIC for which the platform design is configured.

3. The routing structure of claim 1, wherein the transmitter block design is repeated within a platform design for as many transmitter cores as are included in an ASIC for which the platform design is configured, and the transmitter block designs are laid out in groups of two columns.

4. The routing structure of claim 1, wherein the transmitter block design is repeated within a platform design for as many transmitter cores as are included in an ASIC for which the platform design is configured, and the transmitter block designs are laid out in groups of two columns, where a first transmitter block design in a row and a first of the two columns is a mirror image of the transmitter block design in the row and a second of the two columns.

5. The routing structure of claim 1, wherein the transmitter block design is repeated within a platform design for as many transmitter cores as are included in an ASIC for which the platform design is configured, and the transmitter block designs are laid out in groups of two columns with a column of power contacts between the groups of two columns.

6. The routing structure of claim 1, wherein the transmitter block design is repeated within a platform design for as many transmitter cores as are included in an ASIC for which the platform design is configured, and the transmitter block designs are laid out in groups of two columns with a column of ground contacts between the groups of two columns.

7. The routing structure of claim 1, wherein the transmitter block design is repeated within a platform design for as many transmitter cores as are included in an ASIC for which the platform design is configured, and the transmitter block designs are laid out in groups of two columns with a column of power contacts and a column of ground contacts between the groups of two columns.

8. The routing structure of claim 1, wherein the receiver block design is repeated within a platform design for as many receiver cores as are included in an ASIC for which the platform design is configured.

9. The routing structure of claim 1, wherein the receiver block design is repeated within a platform design for as many receiver cores as are included in an ASIC for which the platform design is configured, and the receiver block designs are laid out in groups of two columns.

10. The routing structure of claim 1, wherein the receiver block design is repeated within a platform design for as many receiver cores as are included in an ASIC for which the platform design is configured, and the receiver block designs are laid out in groups of two columns, where a first receiver block design in a row and a first of the two columns is a mirror image of the receiver block design in the row and a second of the two columns.

11. The routing structure of claim 1, wherein the receiver block design is repeated within a platform design for as many receiver cores as are included in an ASIC for which the platform design is configured, and the receiver block designs are laid out in groups of two columns with a column of power contacts between the groups of two columns.

12. The routing structure of claim 1, wherein the receiver block design is repeated within a platform design for as many receiver cores as are included in an ASIC for which the platform design is configured, and the receiver block designs are laid out in groups of two columns with a column of ground contacts between the groups of two columns.

13. The routing structure of claim 1, wherein the receiver block design is repeated within a platform design for as many receiver cores as are included in an ASIC for which the platform design is configured, and the receiver block designs are laid out in groups of two columns with a column of power contacts and a column of ground contacts between the groups of two columns.

14. A routing structure for a transceiver core, comprising:

a transmitter block design within a transmitter design boundary, the transmitter block design including only two dedicated transmitter power contacts, only two common ground contacts, and only two transmitter signal contacts in a transmitter differential pair, and no other contacts within the transmitter design boundary, where the two transmitter signal contacts are both adjacent each of the two dedicated transmitter power contacts and each of the two common ground contacts, and

a receiver block design within a receiver block design boundary, the receiver block design including only two dedicated receiver power contacts, only two common ground contacts, and only two receiver signal contacts in a receiver differential pair, and no other contacts within the receiver design boundary, where the two receiver signal contacts are both adjacent each of the two dedicated receiver power contacts and each of the two common ground contacts.

15. The routing structure of claim 14, wherein the contacts of the transmitter block design are disposed in an array of two columns and three rows, with one each of the dedicated transmitter power contacts and the common ground contacts in a first row, the two transmitter signal contacts in a second row, and one each of the dedicated transmitter power contacts and the common ground contacts in a third row.

16. The routing structure of claim 14, wherein the contacts of the transmitter block design are disposed in an array of two columns and three rows, with one of the dedicated transmitter power contacts in a first column in a first row, one of the common ground contacts in a second column in the first row, the two transmitter signal contacts in a second row, one of the dedicated transmitter power contacts in the second column in a third row, and one of the common ground contacts in the first column in the third row.

17. The routing structure of claim 14, wherein the contacts of the receiver block design are disposed in an array of two columns and three rows, with one each of the dedicated receiver power contacts and the common ground contacts in a first row, the two receiver signal contacts in a second row, and one each of the dedicated receiver power contacts and the common ground contacts in a third row.

18. The routing structure of claim 14, wherein the contacts of the receiver block design are disposed in an array of two columns and three rows, with one of the dedicated receiver power contacts in a first column in a first row, one of the common ground contacts in a second column in the first row, the two receiver signal contacts in a second row, one of the dedicated receiver power contacts in the second column in a third row, and one of the common ground contacts in the first column in the third row.

19. A platform including a routing structure for a transceiver core, the routing structure comprising:

a transmitter block design including two dedicated transmitter power contacts, two common ground contacts, and two transmitter signal contacts in a transmitter differential pair, where the two transmitter signal contacts are both adjacent each of the two dedicated transmitter power contacts and each of the two common ground contacts, and

a receiver block design including two dedicated receiver power contacts, two common ground contacts, and two receiver signal contacts in a receiver differential pair, where the two receiver signal contacts are both adjacent each of the two dedicated receiver power contacts and each of the two common ground contacts.

20. A packaged integrated circuit including the platform of claim 19.