Reducing the effects of neel coupling in MRAM structures

• US 20040217399A1
• Filed: 04/29/2003
• Published: 11/04/2004
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Drewes, Joel A.
• Granted Patent: US 6,900,489 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 10/3268 the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
• CPC Class Codes: H01F 10/3272 by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A magnetic memory element has reduced Néel coupling between a pinned layer and a free layer. The magnetic memory element includes a first pinned ferromagnet and a free ferromagnet which are separated by a barrier layer. The magnetic field direction of the pinned layer is fixed, for example, by an antiferromagnetic exchange layer. An additional ferromagnetic layer, provided in coupling relationship with the first pinned ferromagnet, offsets Néel coupling between the free ferromagnetic layer and the first pinned ferromagnet.

Claims

1. A magnetic memory element comprising:

a pinned ferromagnetic layer maintained in a single stable magnetic polarity state;

a pinning structure for maintaining the stable magnetic polarity state of the pinned ferromagnetic layer;

a free ferromagnetic layer;

a barrier layer between the pinned and the free layers; and

an additional ferromagnetic layer on a side of the pinning structure opposite the pinned ferromagnetic layer.

2. A memory element as in claim 1, wherein the pinning structure comprises an antiferromagnetic exchange layer made up of one of IrMn and PtMn.

3. A memory element as in claim 1, wherein the memory element has no shape-induced anisotropy.

4. A memory element as in claim 1, wherein at least one of the free and pinned layers comprises a layer of at least one of Co—

Fe and Ni—

Fe.

5. A memory element as in claim 1, further comprising conductive layers in electrical contact with the free layer and the additional ferromagnetic layer.

6. A memory element as in claim 1, wherein a ratio of a length of the memory element to a width of the memory element is less than or equal to about 1.2.

7. A magnetic tunnel junction device having memory elements comprising:

a first pinned ferromagnetic layer having a magnetic polarity maintained in a single, stable state;

an antiferromagnetic exchange layer for pinning the polarity of the first pinned ferromagnetic layer;

a free ferromagnetic layer;

a tunnel junction barrier layer between the first pinned ferromagnetic layer and the free layer; and

a second pinned ferromagnetic layer on a side of the antiferromagnetic exchange layer opposite the first pinned ferromagnetic layer, the second pinned ferromagnetic layer offsets Né

el-type coupling between the free layer and the first pinned ferromagnetic layer.

8. A magnetic tunnel junction device as in claim 7, wherein the antiferromagnetic exchange layer comprises at least one of IrMn and PtMn.

9. A magnetic tunnel junction device as in claim 7, further comprising conductive layers in electrical contact with the free layer and the second pinned ferromagnetic layer.

10. A magnetic random access memory including an array of memory elements, each memory element comprising:

a first pinned ferromagnetic layer having a stable magnetic polarity;

a free ferromagnetic layer;

a barrier layer between the first pinned ferromagnetic layer and the free ferromagnetic layer;

an antiferromagnetic exchange layer for pinning the first pinned ferromagnetic layer, and

a second pinned ferromagnetic layer disposed on a side of the antiferromagnetic exchange layer opposite the first pinned ferromagnetic layer.

11. A magnetic random access memory as in claim 10, wherein the antiferromagnetic exchange layer in each memory element comprises a layer of at least one of IrMn and PtMn.

12. A magnetic random access memory as in claim 10, wherein the memory elements have no shape-induced anisotropy.

14. A magnetic random access memory as in claim 10, further comprising conductive layers in electrical contact with the free layer and the offset layer.

15. A magnetic random access memory as in claim 10, wherein the memory elements are arranged separately in a row and column array.

13. (canceled)

16. A processor system comprising:

a processor; and

a magnetic random access memory device for exchanging data with the processor, the memory device comprising an array of memory elements, each memory element comprising;

a first pinned ferromagnetic layer;

an antiferromagnetic exchange layer for pinning the first pinned ferromagnetic layer;

a free ferromagnetic layer;

a barrier layer separating the first pinned ferromagnetic layer and the free ferromagnetic layer; and

a second pinned ferromagnetic layer on a side of the antiferromagnetic exchange layer opposite the first pinned ferromagnetic layer.

17. A processor system as in claim 16, wherein the memory elements have no shape-induced anisotropy.

18. A processor system comprising:

a processor; and

a magnetic random access memory device for exchanging data with the processor, the memory device comprising an array of memory elements, each memory element comprising;

a barrier layer separating a first pinned ferromagnetic layer and a free ferromagnetic layer; and

a second pinned ferromagnetic layer for offsetting Né

el-type coupling between the free ferromagnetic layer and the first pinned ferromagnetic layers and disposed on a side of the first pinned ferromagnetic layer opposite the free ferromagnetic layer.

19. A processor system as in claim 18, wherein the memory elements have no shape-induced anisotropy.

20-24. -24. (canceled)

25. A magnetic memory element comprising:

a pinned structure with a fixed magnetic moment orientation, the pinned structure including first and second ferromagnetic layers, and an antiferromagnetic layer between the first and second ferromagnetic layers;

a free structure with a changeable magnetic moment orientation, the free structure including at least one free ferromagnetic layer and disposed adjacent the pinned structure; and

a barrier layer between the pinned structure and the free structure.

26. The magnetic memory element of claim 25, wherein the memory element has no shape-induced anisotropy.

27. A magnetic memory element comprising:

a seed layer;

a free ferromagnetic structure formed on the seed layer;

a pinned ferromagnetic structure;

a tunnel barrier structure between the free ferromagnetic structure and the pinned ferromagnetic structure;

an antiferromagnetic exchange structure adjacent the pinned ferromagnetic structure; and

an additional pinned ferromagnetic structure formed adjacent the antiferromagnetic exchange structure on a side opposite the pinned ferromagnetic structure, wherein the magnetic memory element has no shape-induced anisotropy, the additional pinned ferromagnetic structure controlling Né

el-type coupling between ferromagnetic structures in the magnetic memory element.

28-34. -34. (canceled)

35. A magnetic random access memory including an array of memory elements, each memory element comprising:

a pinned structure with a fixed magnetic moment orientation, the pinned structure including first and second ferromagnetic layers, and an antiferromagnetic layer between the first and second ferromagnetic layers;

a free structure with a changeable magnetic moment orientation, the free structure including at least one free ferromagnetic layer and disposed adjacent the pinned structure; and

a barrier layer between the pinned structure and the free structure.

36. A processor system comprising:

a processor; and

a magnetic random access memory device for exchanging data with the processor, the memory device comprising an array of memory elements, each memory element comprising;

a pinned structure with a fixed magnetic moment orientation, the pinned structure including first and second ferromagnetic layers, and an antiferromagnetic layer between the first and second ferromagnetic layers;

a free structure with a changeable magnetic moment orientation, the free structure including at least one free ferromagnetic layer and disposed adjacent the pinned structure; and

a barrier layer between the pinned structure and the free structure.