DMOS device having a trenched bus structure
First Claim
1. A trenched DMOS device formed atop an N+ silicon substrate with an N epitaxial layer thereon including a device region and a bus region neighboring the device region, the device region comprising:
- a P substrate, formed in the epitaxial layer and extending to a top surface thereof, a plurality of DMOS trenches extending downward through the P substrate from a top surface thereof;
a gate oxide layer formed in the DMOS trenches and extending to cover the top surface of the P substrate;
a plurality of polysilicon gates formed in the DMOS trenches;
a plurality of N+ source regions formed in the P substrate adjacent the DMOS trenches;
a plurality of P+ diffused regions formed in the P substrate and each being interposed between two of the N+ source regions;
a first isolation layer formed over the P substrate to cover the polysilicon gate electrodes; and
a source metal contact layer formed on the first isolation layer and connecting to the N+ source regions and the P+ diffused regions;
and the bus region comprising;
a P substrate, formed in the epitaxial layer and extending to a top surface of the epitaxial layer, a field oxide layer being formed on the P substrate and a bus trench extending down from a top surface of the field oxide layer to a lower portion of the P substrate;
a gate oxide layer formed in the bus trench and extending to cover a top surface of the P substrate;
a polysilicon bus formed in the bus trench and having a top surface disposed at a lower level than the top surface of the field oxide layer;
a second isolation layer covering the field oxide layer and having an opening to expose the polysilicon bus; and
a metal line formed atop the polysilicon bus.
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Accused Products
Abstract
A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.
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Citations
20 Claims
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1. A trenched DMOS device formed atop an N+ silicon substrate with an N epitaxial layer thereon including a device region and a bus region neighboring the device region, the device region comprising:
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a P substrate, formed in the epitaxial layer and extending to a top surface thereof, a plurality of DMOS trenches extending downward through the P substrate from a top surface thereof;
a gate oxide layer formed in the DMOS trenches and extending to cover the top surface of the P substrate;
a plurality of polysilicon gates formed in the DMOS trenches;
a plurality of N+ source regions formed in the P substrate adjacent the DMOS trenches;
a plurality of P+ diffused regions formed in the P substrate and each being interposed between two of the N+ source regions;
a first isolation layer formed over the P substrate to cover the polysilicon gate electrodes; and
a source metal contact layer formed on the first isolation layer and connecting to the N+ source regions and the P+ diffused regions;
and the bus region comprising;
a P substrate, formed in the epitaxial layer and extending to a top surface of the epitaxial layer, a field oxide layer being formed on the P substrate and a bus trench extending down from a top surface of the field oxide layer to a lower portion of the P substrate;
a gate oxide layer formed in the bus trench and extending to cover a top surface of the P substrate;
a polysilicon bus formed in the bus trench and having a top surface disposed at a lower level than the top surface of the field oxide layer;
a second isolation layer covering the field oxide layer and having an opening to expose the polysilicon bus; and
a metal line formed atop the polysilicon bus. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device set which comprises at least two types of devices, each of the two types of devices having a trench feature;
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wherein the first device comprises a gate oxide formed in the trench feature, a polysilicon layer formed on the gate oxide in the trench features, a first isolation layer formed on the polysilicon layer and having an opening, and a metal layer formed on the first isolation layer and filling the opening of the first isolation layer; and
wherein the second device comprises a dielectric layer formed adjacent an opening at a top of the trench feature on opposite sides of the trench feature, a gate oxide formed in the trench feature and over the dielectric layer, a polysilicon layer formed on the gate oxide in the trench feature including a space near the top of the trench feature with the dielectric layer disposed on opposite sides thereof, a second isolation layer formed on the dielectric layer, and a metal layer formed on the polysilicon layer. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of forming a trenched DMOS device, the method comprising:
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providing an N+ silicon substrate with an N epitaxial layer thereon, and a P substrate in the N epitaxial layer extending to a top surface thereof;
forming in a device region a plurality of DMOS trenches extending downward through the P substrate from a top surface thereof, and in a bus region a field oxide layer on the P substrate and a bus trench extending down from a top surface of the field oxide layer to a lower portion of the P substrate;
forming a gate oxide layer in the DMOS trenches which extends to cover the top surface of the P substrate adjacent the DMOS trenches, and a gate oxide layer in the bus trench which extends to cover the top surface of the P substrate adjacent the bus trench;
forming a plurality of polysilicon gates in the DMOS trenches, and a polysilicon bus in the bus trench, the polysilicon bus having a top surface disposed at a lower level than the top surface of the field oxide layer;
forming a plurality of N+ source regions in the P substrate adjacent the DMOS trenches;
forming a plurality of P+ diffused regions in the P substrate, each of the P+ diffused regions being interposed between two of the N+ source regions;
forming a first isolation layer over the P substrate to cover the polysilicon gates, and a second isolation layer to cover the field oxide layer, the second isolation layer having an opening to expose the polysilicon bus; and
forming a source metal contact layer on the first isolation layer, and a metal line atop the polysilicon bus, the source metal contact layer connecting to the N+ source regions and the P+ diffused regions. - View Dependent Claims (17, 18, 19, 20)
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Specification