Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same

• US 20040217434A1
• Filed: 04/30/2004
• Published: 11/04/2004
• Est. Priority Date: 05/02/2003
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sung-Min, Lee, Sung-Young, Park, Dong-Gun, Yeo, Kyoung-Hwan
• Application Number:
  US10/835,760
• Publication Number:
  US 20040217434A1
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/802 with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors H01L29/806 takes precedence; with one dimensional electron gas H01L29/775; with dimensional electron gas H01L29/778

Abstract

An integrated circuit device includes a substrate. An epitaxial pattern is on the substrate and has a pair of impurity diffusion regions formed therein and a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate. Respective ones of the pair of impurity diffusion regions at least partially overlap respective ones of the pair of void regions. A gate electrode is on the epitaxial pattern between respective ones of the pair of impurity diffusion regions.

Claims

1. An integrated circuit device, comprising:

a substrate;

an epitaxial pattern on the substrate having a pair of impurity diffusion regions formed therein and a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate, respective ones of the pair of impurity diffusion regions at least partially overlapping respective ones of the pair of void regions; and

a gate electrode on the epitaxial pattern between respective ones of the pair of impurity diffusion regions.

2. The integrated circuit device of claim 1, wherein the epitaxial pattern is directly on the substrate.

3. The integrated circuit device of claim 1, wherein the epitaxial pattern comprises silicon and/or silicon-germanium.

4. The integrated circuit device of claim 1, wherein the gate electrode comprises polysilicon and/or metal silicide.

5. The integrated circuit of claim 1, wherein the pair of void regions are filled with an insulating material.

6. The integrated circuit of claim 1, further comprising:

a device isolation layer adjacent to the epitaxial pattern that has an upper surface, opposite the substrate, that is lower than an upper surface of the epitaxial pattern, opposite the substrate.

7. An integrated circuit device, comprising:

a substrate;

an epitaxial pattern on the substrate having a pair of impurity diffusion regions formed therein and a void region formed therein between respective ones of the pair of impurity diffusion regions; and

a gate electrode on the epitaxial pattern between respective ones of the pair of impurity diffusion regions, the gate electrode at least partially overlapping the void region.

8. The integrated circuit device of claim 7, wherein the epitaxial pattern is directly on the substrate.

9. The integrated circuit device of claim 7, wherein the epitaxial pattern comprises silicon and/or silicon-germanium.

10. The integrated circuit device of claim 7, wherein the gate electrode comprises polysilicon and/or metal silicide.

11. The integrated circuit of claim 7, wherein the void region is filled with an insulating material.

12. The integrated circuit of claim 7, further comprising:

a device isolation layer adjacent to the epitaxial pattern that has an upper surface, opposite the substrate, that is lower than an upper surface of the epitaxial pattern, opposite the substrate.

13. A semiconductor device, comprising:

a semiconductor substrate including a device isolation layer;

an epitaxial pattern on the substrate that forms an empty space region together with the device isolation layer;

a gate electrode on the epitaxial pattern and on the device isolation region; and

impurity diffusion regions formed in the epitaxial pattern at both sides of the gate electrode.

14. The semiconductor device of claim 13, wherein the empty space region is disposed between the epitaxial pattern under the gate electrode and the substrate.

15. The semiconductor device of claim 13, wherein the empty space region is disposed between the epitaxial pattern at both sides of the gate electrode and the substrate.

16. The semiconductor device of claim 13, wherein the device isolation region extends to the empty space region and fills the empty space.

17. The semiconductor device of claim 13, wherein a top surface of the device isolation layer is lower than a top surface of the epitaxial pattern.

18. The semiconductor device of claim 13, wherein the epitaxial pattern comprises silicon and/or silicon-gemanium.

19. A method of fabricating a semiconductor device comprising:

forming an epitaxial sacrificial pattern on a semiconductor substrate;

forming an epitaxial layer on the epitaxial sacrificial pattern and on the substrate exposed by the epitaxial sacrificial pattern;

etching the epitaxial layer, the epitaxial sacrificial pattern, and a partial thickness of the substrate to form an epitaxial pattern from the epitaxial layer and a trench in the substrate;

removing the etched epitaxial sacrificial pattern exposed by the trench;

forming a device isolation region filling the trench such that a top surface of the device isolation region is lower than a top surface of the epitaxial sacrificial pattern;

forming a gate electrode crossing the epitaxial pattern; and

forming impurity diffusion regions in the epitaxial pattern at both sides of the gate electrode.

20. The method of fabricating the semiconductor device of claim 19, wherein forming the epitaxial pattern and a trench for a device isolation comprises:

forming a mask pattern on the epitaxial layer;

etching the epitaxial layer, the epitaxial sacrificial pattern and a partial thickness of the substrate using the mask pattern as an etching mask; and

wherein forming the device isolation region comprises;

forming an insulating material on the mask pattern to fill the trench;

using a planarizing etch of the insulating material until exposing the mask pattern;

removing the exposed mask pattern; and

etching back the insulating materials such that a top surface of the insulating materials is lower than the epitaxial pattern.

21. The method of fabricating the semiconductor device of claim 20, further comprising the following before forming the insulating material:

forming a thermal oxide layer in the etched epitaxial sacrificial pattern and the trench by performing a thermal oxidation process; and

forming a liner nitride layer on the thermal oxide layer.

22. The method of fabricating the semiconductor device of claim 19, wherein the insulating material fills a region where the etched epitaxial sacrificial pattern is removed.

23. The method of fabricating the semiconductor device of claim 19, wherein the region where the etched epitaxial sacrificial pattern is removed is disposed between the epitaxial pattern at both sides of the gate electrode and the substrate.

24. The method of fabricating the semiconductor device of claim 19, wherein the region where the etched epitaxial sacrificial pattern is removed is disposed between the itaxial pattern under the gate electrode and the substrate.

25. The method of fabricating the semiconductor device of claim 19, wherein the epitaxial layer comprises a silicon layer.

26. The method of fabricating the semiconductor device of claim 25, wherein the epitaxial sacrificial layer has the same crystalline structure as silicon and lattice constant similar to silicon.

27. The method of fabricating the semiconductor device of claim 26, wherein the epitaxial sacrificial layer comprises Si—

Ge, CeO₂, and/or CaF₂.

28. The method of fabricating the semiconductor device of claim 19, wherein the epitaxial sacrificial layer comprises Si—

Ge, CeO₂, and/or CaF₂.

29. The method of fabricating the semiconductor device of claim 19, wherein the epitaxial sacrificial layer comprises silicon and the epitaxial layer comprises silicon-germanium.

30. A semiconductor device comprising:

an epitaxial silicon layer electrically connected to a semiconductor substrate and is disposed on the substrate to form an insulating region therebetween;

a gate electrode crossing the epitaxial silicon layer; and

impurity diffusion regions formed on the epitaxial silicon layer at both sides of the gate electrode.

31. The semiconductor device of claim 30, wherein the insulating region is disposed between the impurity diffusion regions and the substrate.

32. The semiconductor device if claim 30, wherein the insulating regions are disposed between the epitaxial silicon layer under the gate electrode and the substrate.

33. An integrated circuit device, comprising:

a substrate;

an epitaxial pattern on the substrate having a pair of impurity diffusion regions formed therein and at least one void region formed therein that is disposed beneath the pair of impurity diffusion regions; and

a gate electrode on the epitaxial pattern between respective ones of the pair of impurity diffusion regions.

34. The integrated circuit device of claim 33, wherein the at least one void region comprises a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate, respective ones of the pair of impurity diffusion regions at least partially overlapping respective ones of the pair of void regions.

35. The integrated circuit device of claim 33, wherein the at least one void region is disposed between respective ones of the pair of impurity diffusion regions, and wherein the gate electrode at least partially overlaps the at least one void region.

36. The integrated circuit device of claim 33, wherein the epitaxial pattern is directly on the substrate.

37. The integrated circuit device of claim 33, further comprising an oxide layer in the at least one void region.

38. The integrated circuit device of claim 37, further comprising a nitride layer on the oxide layer.

39. The integrated circuit device of claim 33, wherein the epitaxial pattern comprises silicon and/or silicon-germanium.

40. The integrated circuit device of claim 33, wherein the gate electrode comprises polysilicon and/or metal silicide.

41. The integrated circuit of claim 33, wherein the at least one void region is filled with an insulating material.

42. The integrated circuit of claim 33, further comprising:

a device isolation layer adjacent to the epitaxial pattern that has an upper surface, opposite the substrate, that is lower than an upper surface of the epitaxial pattern, opposite the substrate.