Semiconductor device with inductive component and method of making

• US 20040217443A1
• Filed: 06/03/2004
• Published: 11/04/2004
• Est. Priority Date: 08/01/2001
• Status: Active Grant

• Current Assignee: David Richard Stanowski
• Original Assignee: Robert B Davies
• Inventors: Davies, Robert B.
• Granted Patent: US 7,078,784 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top surface (49) of the inductor is substantially coplanar with an interconnect surface (31) of the semiconductor substrate, which facilitates connecting to the inductor with standard integrated circuit metallization (57).

Claims

1. An integrated circuit, comprising:

a semiconductor substrate having a dielectric region formed with a trench and an adjacent cavity; and

a conductive material disposed within the trench to produce an inductance.

2. The integrated circuit of claim 1, wherein the dielectric region includes a cap layer formed at a top surface of the semiconductor substrate and the cavity extends from the cap layer to a bottom surface of the dielectric region.

3. The integrated circuit of claim 1, wherein a bottom surface of the semiconductor substrate defines a first recessed region underlying the dielectric region.

4. The integrated circuit of claim 1, wherein the conductive material includes copper.

5. The integrated circuit of claim 1, wherein the conductive material is disposed within the trench to a depth of at least five micrometers.

6. The integrated circuit of claim 1, wherein the dielectric region is formed with a silicon based dielectric.

7. The integrated circuit of claim 1, wherein the dielectric region is formed at a top surface of the semiconductor substrate, further comprising an active device formed at the top surface.

8. A method of making an integrated circuit, comprising the steps of:

forming a dielectric region in a semiconductor substrate to have a cavity and a trench; and

disposing a conductive material within the trench to produce an inductance.

9. The method of claim 8, wherein the step of forming includes the step of forming the dielectric region at a top surface of the semiconductor substrate.

10. The method of claim 8, wherein the step of disposing includes the step of plating the conductive material within the trench to form an inductor.

11. The method of claim 10, wherein the step of plating includes the step of electroplating copper within the trench.

12. The method of claim 10, wherein the step of plating includes the steps of:

applying a plating signal to a bottom surface of the semiconductor substrate; and

coupling the plating signal through the semiconductor substrate to a bottom surface of the trench.

13. The method of claim 12, wherein the step of plating includes the step of depositing a barrier material to form a barrier layer at the bottom surface of the trench.

14. The method of claim 13, wherein the step of depositing includes the step of depositing a metal selected from the group consisting of platinum, titanium and cobalt along the bottom surface of the trench.

15. The method of claim 14, wherein the step of depositing a metal includes the step of forming the barrier layer to include a metal silicide.

16. The method of claim 8, further comprising the step of etching a bottom surface of the semiconductor substrate to form a recessed region underlying the dielectric region.

17. The method of claim 16, wherein the step of etching includes the step of removing material from the bottom surface of the semiconductor substrate extending to a bottom surface of the trench.

18. The method of claim 8, wherein the step of disposing includes the step of disposing the conductive material within the trench to a thickness of at least five micrometers.

19. A method of making an integrated circuit, comprising the steps of:

forming a dielectric region in a semiconductor substrate, where the dielectric region has a cavity;

etching the dielectric region to form a trench adjacent to the cavity; and

disposing a conductive material in the trench to form an inductor.

20. The method of claim 19, wherein the step of etching includes the step of removing dielectric material to a depth of at least five micrometers from the dielectric region.

21. The method of claim 19, wherein the step of disposing includes the step of plating the conductive material within the trench.

22. The method of claim 21, wherein the step of plating includes the step of electroplating copper from a bottom surface of the trench to a top surface of the semiconductor substrate.

23. The method of claim 19, further comprising the step of depositing a barrier material to form an etch stop on a bottom surface of the trench.

24. The method of claim 23, wherein the step of forming includes the step of forming the dielectric region at a top surface of the semiconductor substrate, further comprising the step of etching a second surface of the semiconductor substrate to form a recessed region under the dielectric region.

25. The method of claim 24, wherein the step of etching the second surface includes the step of removing material from the second surface extending to the etch stop to form the recessed region.

26. The method of claim 25, further comprising the step of mounting the semiconductor substrate to a die attach pad.

27. The method of claim 26, wherein the step of mounting includes the step of mounting the recessed region over a pedestal of the die attach pad.

28. A semiconductor device, comprising:

a semiconductor substrate having a dielectric region formed with a cavity;

a first inductor formed within a trench defined by the dielectric region; and

a second inductor overlying the first inductor.

29. The semiconductor device of claim 28, further comprising a transistor formed at a top surface of the semiconductor substrate.

30. The semiconductor device of claim 29, wherein a portion of the first inductor is formed below the top surface.

31. The semiconductor device of claim 28, wherein the first inductor is formed to a thickness of at least five micrometers.

32. The semiconductor device of claim 31, wherein the second inductor is formed to a thickness of at least five micrometers.

33. The semiconductor device of claim 28, further comprising a dielectric layer formed between the first and second inductors.

34. A method of making an integrated circuit, comprising the step of applying a signal to a first surface of a semiconductor substrate to plate an inductor on a second surface of the semiconductor substrate.

35. The method of claim 34, wherein the step of applying includes the steps of:

forming a trench on the first surface; and

coupling a plating voltage from the second surface to a bottom of the trench to deposit a conductive material in the trench as the inductor.

36. The method of claim 34, further comprising the step of forming a transistor on the second surface of the semiconductor substrate.

37. An integrated circuit comprising:

a low resistivity, semiconductor substrate with a planar surface, the substrate including a dielectric region having a portion defined in and extending parallel with the planar surface;

an elongated trench formed in the dielectric region and including side-walls defined by low dielectric constant material, the elongated trench extending parallel with the planar surface of the semiconductor substrate a distance defining one inductor of an inductive device;

high conductivity material positioned in and substantially filling the trench and forming the one inductor of the inductive device; and

a conductive trace on the planar surface electrically connecting the one inductor of the inductive device to external circuitry.

47. An integrated circuit comprising:

a low resistivity, semiconductor substrate with a planar surface, the substrate including an active region and a dielectric region each having a portion defined in and extending parallel with the planar surface;

the dielectric region including a volume filled with dielectric material surrounding and defining an array of cavities, the dielectric material having a first dielectric constant and the cavities providing a second dielectric constant lower than the first dielectric constant to form an effective dielectric constant lower than the first dielectric constant;

at least one active component positioned in the active region;

an elongated trench formed in the dielectric region and including side-walls defined by low dielectric constant material, the elongated trench extending parallel with the planar surface of the semiconductor substrate a distance defining one inductor of an inductive device;

high conductivity material positioned in and substantially filling the trench and forming the one inductor of the inductive device; and

a conductive trace on the planar surface electrically connecting the one inductor of the inductive device and the at least one active component.

48. An integrated circuit as claimed in claim 62 further including a thin conductive barrier layer positioned on an upper surface of the high conductivity material in the trench so as to have an upper surface coplanar with the planar surface of the semiconductor substrate.

49. An integrated circuit as claimed in claim 62 further including a cavity defined at least partially by the substrate and positioned in underlying relationship adjacent the elongated trench, the cavity and the side-walls electrically and spacially separating the one inductor of the inductive device from the semiconductor substrate.

50. An integrated circuit as claimed in claim 62 wherein the inductive device further includes at least a second inductor extending parallel with and in overlying relationship to the planar surface of the semiconductor substrate, the second inductor overlying the first inductor and separated from the first inductor by a layer of dielectric material and the first inductor and the second inductor being wound in the same direction.

51. An integrated circuit comprising:

a low resistivity, semiconductor substrate with a planar surface, the substrate including an active region and a dielectric region each having a portion defined in and extending parallel with the planar surface;

the dielectric region including a volume filled with dielectric material surrounding and defining an array of cavities, the dielectric material having a first dielectric constant and the cavities providing a second dielectric constant lower than the first dielectric constant to form an effective dielectric constant lower than the first dielectric constant;

at least one active component positioned in the active region;

an elongated trench formed in the dielectric region and including side-walls defined by low dielectric constant material, the elongated trench extending parallel with the planar surface of the semiconductor substrate a distance defining one inductor of an inductive device;

high conductivity material positioned in and substantially filling the trench and forming the one inductor of the inductive device;

a cavity defined at least partially by the substrate and positioned in underlying relationship adjacent the elongated trench, the cavity and the side-walls electrically and spacially separating the one inductor of the inductive device from the semiconductor substrate; and

a conductive trace on the planar surface electrically connecting the one inductor of the inductive device and the at least one active component.

52. An integrated circuit as claimed in claim 66 further including a thin conductive barrier layer positioned on an upper surface of the high conductivity material in the trench so as to have an upper surface coplanar with the planar surface of the semiconductor substrate.

38. An integrated circuit as claimed in claim 52 further including at least one active component positioned in an active region of the low resistivity, semiconductor substrate and coupled to the inductive device.

39. An integrated circuit as claimed in claim 52 further including a thin conductive barrier layer positioned on an upper surface of the high conductivity material in the trench so as to have an upper surface coplanar with the planar surface of the semiconductor substrate.

40. An integrated circuit as claimed in claim 52 further including a cavity defined at least partially by the substrate and positioned in underlying relationship adjacent the elongated trench, the cavity and the side-walls electrically and inductively separating the one inductor of the inductive device from the semiconductor substrate.

41. An integrated circuit as claimed in claim 52 wherein the dielectric region includes a volume filled with low dielectric constant material including dielectric material defining an array of cavities therein, the dielectric material having a first dielectric constant and the cavities providing a second dielectric constant lower than the first dielectric constant to form an effective dielectric constant lower than the first dielectric constant.

42. An integrated circuit as claimed in claim 52 wherein the inductive device includes a plurality of similar inductors formed in the dielectric region.

43. An integrated circuit as claimed in claim 52 wherein the inductive device further includes at least a second inductor extending parallel with and in overlying relationship to the planar surface of the semiconductor substrate, the second inductor overlying the first inductor and separated from the first inductor by a layer of dielectric material.

53. An integrated circuit as claimed in claim 66 wherein the inductive device includes a plurality of similar inductors formed in the dielectric region.

54. An integrated circuit as claimed in claim 66 wherein the inductive device further includes at least a second inductor extending parallel with and in overlying relationship to the planar surface of the semiconductor substrate, the second inductor overlying the first inductor and separated from the first inductor by a layer of dielectric material.

55. An integrated circuit as claimed in claim 69 wherein the first inductor and the second inductor are wound in the same direction.

56. An integrated circuit as claimed in claim 70 wherein the inductive device includes a transformer.

57. An integrated circuit as claimed in claim 69 wherein the high conductivity material positioned in and substantially filling the trench defining the first inductor includes electroplated copper and the second inductor includes electroplated copper.

58. An integrated circuit comprising:

a semiconductor substrate with a planar surface, the substrate including a dielectric region having a portion defined in and extending parallel with the planar surface;

an elongated trench formed in the dielectric region and including side-walls defined by low dielectric constant material, the elongated trench extending parallel with the planar surface of the semiconductor substrate a distance defining at least one inductor of an inductive device;

high conductivity material positioned in and substantially filling the trench and forming the one inductor of the inductive device;

at least a second inductor extending parallel with and in overlying relationship to the planar surface of the semiconductor substrate, the second inductor overlying the first inductor and separated from the first inductor by a layer of dielectric material; and

the first inductor and the second inductor being wound in the same direction.

44. An integrated circuit as claimed in claim 58 wherein the first inductor and the second inductor are wound in the same direction.

46. An integrated circuit as claimed in claim 58 wherein the high conductivity material positioned in and substantially filling the trench defining the first inductor includes electroplated copper and the second inductor includes electroplated copper.

59. An integrated circuit as claimed in claim 69 wherein the inductive device includes a plurality of first inductors and a plurality of second inductors interconnected to form a single inductive device.

45. An integrated circuit as claimed in claim 59 wherein the inductive device includes a transformer.