Sequencing power supplies on daughter boards

• US 20040217651A1
• Filed: 05/02/2003
• Published: 11/04/2004
• Est. Priority Date: 05/02/2003
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Potentia Semiconductor, Inc.
• Inventors: Brown, David Alan, Guher, Muge
• Granted Patent: US 7,080,273 B2
• Time in Patent Office: Days
• US Class Current: 307/31
• CPC Class Codes: H02J 1/102 being switching converters H02J1/108, H02J1/12 take precedence
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters

Abstract

Power supplies are enabled and disabled in sequence by a controller in dependence upon output voltages of the power supplies monitored by the controller. The controller allows proper sequencing of the power supplies when one or more of them is provided on a daughter board, when this is not connected to a mother board on which the controller is provided, by storing information as to any power supply provided on the daughter board, detecting when the daughter board is not connected to the mother board, and in that case enabling the power supplies in sequence independently of any monitored output voltage of such a power supply on the daughter board.

Claims

1. A method of controlling a plurality of power supplies, comprising the steps of:

controlling the plurality of power supplies in a predetermined sequence using a power supply controller on a mother board, the control being dependent upon monitored output voltages of the power supplies;

providing at least one of the power supplies on a daughter board which can be connected to the mother board;

detecting whether or not the daughter board is connected to the mother board; and

over-riding the dependence of the control on a monitored output voltage of a power supply on the daughter board in response to detecting that the daughter board is not connected to the mother board.

2. A method as claimed in claim 1 wherein the step of over-riding the dependence of the control on a monitored output voltage of a power supply on the daughter board comprises identifying in the power supply controller each power supply on the daughter board, and over-riding the dependence of the control on the monitored output voltage of each identified power supply on the daughter board in response to detecting that the daughter board is not connected to the mother board.

3. A method as claimed in claim 1 wherein the step of over-riding the dependence of the control on a monitored output voltage of a power supply on the daughter board comprises storing in a respective bit position of a configuration register an indication of each of the plurality of power supplies, and storing in a corresponding bit position of another register an indication of each power supply provided on the daughter board.

4. A method as claimed in claim 1 wherein the step of detecting whether or not the daughter board is connected to the mother board comprises biassing an input of the power supply controller to a first logic level when the daughter board is not connected to the mother board, and supplying a second logic level to said input via a connection between the mother board and the daughter board when the daughter board is connected to the mother board.

5. A method as claimed in claim 1 wherein the step of controlling the plurality of power supplies in a predetermined sequence comprises enabling the power supplies in a power-up sequence.

6. A method as claimed in claim 1 wherein the step of controlling the plurality of power supplies in a predetermined sequence comprises disabling the power supplies in a power-down sequence.

7. A method as claimed in claim 3 wherein the step of controlling the plurality of power supplies in a predetermined sequence comprises enabling the power supplies in a power-up sequence.

8. A method as claimed in claim 7 and comprising the step of storing, in a respective register for each of the plurality of power supplies, an indication in a respective bit position of a preceding power supply in the power-up sequence, the respective bit positions corresponding to the respective bit positions of the configuration register.

9. A method as claimed in claim 3 wherein the step of controlling the plurality of power supplies in a predetermined sequence comprises disabling the power supplies in a power-down sequence.

10. A method as claimed in claim 9 and comprising the step of storing, in a respective register for each of the plurality of power supplies, an indication in a respective bit position of a preceding power supply in the power-down sequence, the respective bit positions corresponding to the respective bit positions of the configuration register.

11. A method of enabling a plurality of power supplies in a predetermined power-up sequence, comprising the steps of:

providing on a mother board a power supply controller for monitoring output voltages of the power supplies and for enabling the power supplies in said power-up sequence in dependence upon the monitored output voltages;

providing at least one of the power supplies on a daughter board which can be connected to the mother board;

detecting whether or not the daughter board is connected to the mother board; and

in response to detecting that the daughter board is not connected to the mother board, enabling the power supplies in said power-up sequence independently of a monitored output voltage of a power supply on the daughter board.

12. A method as claimed in claim 11 wherein the step of enabling the power supplies comprises storing in a respective bit position of a configuration register an indication of each of the plurality of power supplies, storing in a corresponding bit position of another register an indication of each power supply provided on the daughter board, and storing, in a corresponding bit position of a respective register for each of the plurality of power supplies, an indication of a preceding power supply in the power-up sequence.

13. A method as claimed in claim 11 wherein the step of detecting whether or not the daughter board is connected to the mother board comprises biassing an input of the power supply controller to a first logic level when the daughter board is not connected to the mother board, and supplying a second logic level to said input via a connection between the mother board and the daughter board when the daughter board is connected to the mother board.

14. A method as claimed in claim 11 and further comprising the step of disabling the plurality of power supplies in a predetermined power-down sequence, the step of disabling comprising the steps of:

disabling the power supplies in said power-down sequence in dependence upon the monitored output voltages; and

in response to detecting that the daughter board is not connected to the mother board, disabling the power supplies in said power-down sequence independently of a monitored output voltage of a power supply on the daughter board.

18. A circuit arrangement comprising:

a mother board;

a daughter board which can be connected to the mother board;

a plurality of power supplies on said boards, at least one of the power supplies being provided on the daughter board;

a power supply controller for carrying out the method of claim 11, the power supply controller comprising at least one control unit for monitoring said output voltages and for enabling each of said power supplies; and

a detection circuit coupled to an input of the control unit for detecting whether or not the daughter board is connected to the mother board.

15. A method of enabling a plurality of power supplies in a predetermined power-up sequence, comprising the steps of:

providing on a mother board a power supply controller for monitoring output voltages of the power supplies;

providing at least one of the power supplies on a daughter board which can be connected to the mother board; and

detecting whether or not the daughter board is connected to the mother board;

wherein the power supply controller enables the power supplies in said power-up sequence in dependence upon the monitored output voltages of power supplies on the mother board, and in dependence upon the monitored output voltages of power supplies on the daughter board only in response to detecting that the daughter board is connected to the mother board.

16. A method as claimed in claim 15 and further comprising the step of disabling the plurality of power supplies in a predetermined power-down sequence, wherein the power supply controller disables the power supplies in said power-down sequence in dependence upon the monitored output voltages of power supplies on the mother board, and in dependence upon the monitored output voltages of power supplies on the daughter board only in response to detecting that the daughter board is connected to the mother board.

17. A method as claimed in claim 16 wherein the power-down sequence is opposite to the power-up sequence.