Propagation delay adjustment circuit

• US 20040217794A1
• Filed: 04/30/2003
• Published: 11/04/2004
• Est. Priority Date: 04/30/2003
• Status: Abandoned Application

• Current Assignee: EDC Biosystems, Inc.
• Original Assignee: EDC Biosystems, Inc.
• Inventors: Strysko, Mark
• Application Number:
  US10/427,557
• Publication Number:
  US 20040217794A1
• Time in Patent Office: Days
• US Class Current: 327/263
• CPC Class Codes: H03H 11/265 with adjustable delay
• CPC Class Codes: H03H 7/345 Adjustable networks
• CPC Class Codes: H03K 2005/00293 Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

Disclosed is a method and apparatus for variably and independently delaying the rising and falling edges of a digital waveform including a dual polarity output buffer, a first delay circuit, a second delay circuit and a recombination circuit. The dual polarity output buffer outputs a first signal that is a substantial replica of the input signal and a second signal that is an inversion of the input signal. The first delay circuit is connected to the dual polarity output buffer and generates a first time delay in the rising edges of the first, non-inverted signal. The second delay circuit is also connected to the dual polarity output buffer and generates a second time delay in the rising edges of the second, inverted signal. The recombination circuit is connected to both the first delay circuit and the second delay circuit and combines the outputs thereof to generate a composite output signal representing the input signal with both the rising edges thereof and the falling edges thereof delayed independently.

Claims

1. A circuit arrangement for delaying both a rising edge and a falling edge of an input signal including:

a dual polarity output buffer for generating a first signal and a second signal, the first signal being a substantial replica of the input signal and the second signal being a substantial inversion of the input signal;

a first delay circuit interconnected to the dual polarity output buffer for causing a first time delay in the rising edge of the first signal;

a second delay circuit interconnected to the dual polarity output buffer for causing a second time delay in the rising edge of the second signal; and

a recombination circuit interconnected to both the first delay circuit and the second delay circuit and which combines an output of the first delay circuit and an output of the second delay circuit to generate a composite output signal representing the input signal with both the rising edge thereof and the falling edge thereof delayed.

2. The circuit arrangement of claim 1 wherein the input signal is a digital waveform.

3. The circuit arrangement of claim 1 wherein the delay in the rising edge of the composite output signal can be varied independently from the delay in the falling edge of the composite output signal.

4. The circuit arrangement of claim 1 wherein the dual polarity output buffer includes a circuit input, and the first delay circuit includes a first delay input which is connected to the circuit input.

5. The circuit arrangement of claim 1 wherein the dual polarity output buffer includes a first comparator having a non-inverting output and an inverting output wherein the non-inverting output is connected to the first delay circuit and the inverting output is connected to the second delay circuit.

6. The circuit arrangement of claim 1 wherein the first delay circuit includes a first RC circuit, a dc reference, and a second comparator having a first input driven by the first RC circuit and a second input driven by the dc reference wherein the first time delay is determined by the point at which a voltage level of an output of the RC circuit exceeds a voltage level of an output of the dc reference.

7. The circuit arrangement of claim 6 wherein the dc voltage level generated by the dc reference is variable and varying the dc voltage generated by the dc reference varies the first time delay caused by the first delay circuit.

8. The circuit arrangement of claim 6 wherein a rise time of a signal generated by the RC circuit is variable and varying the rise time of a signal generated by the RC circuit varies the first time delay caused by the first delay circuit.

9. The circuit arrangement of claim 6 wherein the second delay circuit is a substantial duplicate of the first delay circuit.

10. The circuit arrangement of claim 1 wherein the recombination circuit includes:

a logical OR gate having a first input driven by the first delay circuit; and

a second input driven by the second delay circuit such that rising edge timing of an output signal of the logical OR gate is alternately determined by the output of the first delay circuit and the output of the second delay circuit.

11. The circuit arrangement of claim 10 wherein the recombination circuit includes a flip-flop driven by the logical OR gate output signal, the flip-flop generating a flip-flop output signal having a rising edge delay determined by a first set of alternate rising edges of the logical OR gate output signal and a falling edge delay determined by a second set of alternate rising edges of the logical OR gate output signal.

12. A method of generating a signal having a delayed rising edge and a delayed falling edge with respect to an input signal including:

inverting the input signal to create an inverted signal delaying a rising edge of the input signal by driving a first delay circuit with the input signal;

delaying a rising edge of the inverted signal by driving a second delay circuit with the inverted signal; and

combining an output of the first delay circuit and an output of the second delay circuit to generate a composite signal representing the input signal with both the rising edge and the falling edge delayed.

13. The method of claim 12 wherein the input signal is a digital waveform.

14. The method of claim 12 wherein the step of combining an output of the first delay circuit and an output of the second delay circuit includes generating a composite signal having a first variable delay in a rising edge thereof and a second variable delay in a falling edge thereof.

15. The method of claim 14 wherein the first variable delay is equal to the second variable delay.

16. The method of claim 14 wherein the first variable delay is not equal to the second variable delay.

17. The method of claim 12 wherein the step of delaying the rising edges of the input signal includes:

generating an intermediate signal from the input signal, the intermediate signal having a ramping portion;

comparing the level of the ramping portion of the intermediate signal with a predetermined de reference level; and

generating a digital waveform rising edge on an output signal when the level of the ramping portion of the intermediate signal exceeds the predetermined dc reference level.

18. The method of claim 17 wherein the step of generating an intermediate signal includes generating an intermediate signal having a variable non-linear rising edge.

19. The method of claim 12 wherein the step of combining an output of the first delay circuit and an output of the second delay circuit includes:

generating an intermediate signal having a rising edge delay alternately determined by the rising edge delay of the input signal and the rising edge delay of the inverted signal; and

generating the composite output signal having rising edge timing determined by a first set of alternate rising edges of the intermediate signal and falling edge timing determined by a second set of alternate rising edges of the intermediate signal.