Integrated inductor and electronic circuit incorporating the same

• US 20040217839A1
• Filed: 02/06/2004
• Published: 11/04/2004
• Est. Priority Date: 02/07/2003
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Clement, Cecile, Haaren, Bart Van, Gloria, Daniel
• Granted Patent: US 7,057,488 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49071 by winding or coiling

Abstract

An integrated inductor comprises a first substantially plane conducting track made on the surface of a substrate and having a shape which defines a predetermined number N of concentric turns. A first pair of access points corresponds to the two respective ends of the said first conducting track. In addition, at least a second pair of access points different from the access points of the first pair, are placed at two respective regions of the first conducting track.

Claims

1. Substantially plane integrated inductor made on the surface of a substrate, comprising a first conducting track having a shape which defines a predetermined number N of concentric turns, and comprising a first pair of access points corresponding to the two respective ends of the said first conducting track,

and further comprising at least a second pair of access points different from the access points of the first pair, and placed at two respective regions of the first conducting track.

2. Integrated inductor according to claim 1, wherein the shape of the first conducting track has an axial symmetry of a determined axis, the said determined axis being the perpendicular bisector of the segment formed by the access points of the first pair of access points.

3. Integrated inductor according to claim 2, wherein the said axis of symmetry of the first conducting track is in addition the perpendicular bisector of the segment formed by the access points of the second pair of access points.

4. Integrated inductor according to claim 2, further comprising a second substantially straight conducting track having an axis coincident with the axis of symmetry of the first conducting track, and electrically connected to the first conducting track in a region corresponding to the middle of the extended length of the said first conducting track, together with a first additional access point corresponding to a first end of the second conducting track.

5. Integrated inductor according to claim 4, further comprising a second additional access point corresponding to a second end of the second conducting track.

6. Integrated inductor according to claim 1, wherein the access points of the second pair of access points are located respectively at approximately one quarter and three quarters of the extended length of the first conducting track.

7. Integrated inductor according to claim 1, wherein the turns of the first conducting track are polygonal.

8. Integrated inductor according to claim 7, wherein the turns of the first conducting track are octagonal.

9. An integrated electronic circuit comprising a substantially plane integrated inductor made on the surface of a substrate, comprising a first conducting track having a shape which defines a predetermined number N of concentric turns, and comprising a first pair of access points corresponding to the two respective ends of the said first conducting track,

and further comprising at least a second pair of access points different from the access points of the first pair, and placed at two respective regions of the first conducting track.

10. Integrated electronic circuit according to claim 9 further comprising means for applying currents in phase opposition respectively to each of the access points of the first pair of access points, and means for applying currents in phase opposition respectively to each of the access points of at least one of a second pair of access points, a first additional access point and a second additional access point being taken to a neutral electrical potential.