Arrangement for energy conditioning

• US 20040218332A1
• Filed: 12/10/2003
• Published: 11/04/2004
• Est. Priority Date: 04/08/1997
• Status: Active Grant

• Current Assignee: X2Y Attenuators, LLC
• Original Assignee: X2Y Attenuators, LLC
• Inventors: Anthony, Anthony A, Anthony, William M
• Granted Patent: US 7,336,468 B2
• Time in Patent Office: Days
• US Class Current: 361/118
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 9/00 Screening of apparatus or components against electric or magnetic fields devices for absorbing radiation from an antenna H01Q17/00
• CPC Class Codes: H05K 9/0071 Active shielding
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49194 Assembling elongated conductors, e.g., splicing, etc.

Abstract

Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Claims

1. A device, comprising:

at least a first and a second plurality of pathways;

wherein said first plurality further comprises at least two pathways arranged electrically isolated from each other and orientated in a first complementary relationship;

wherein at least a first number of pathways of said second plurality is arranged electrically isolated from a second number of pathways of said second plurality; and

wherein the at least two pathways of said second plurality are electrically isolated from said first plurality.

2. The device of claim 1, wherein at least two pathways of said first number of pathways of said second plurality are electrically coupled to one another;

and

wherein at least two pathways of said second number of pathways of said second plurality are electrically coupled to one another.

3. The device of claim 1, wherein said first number of pathways of said second plurality is an odd number greater than one;

wherein said second number of pathways of said second plurality is an odd number greater than one;

wherein at least two pathways of said first number of pathways of said second plurality are electrically coupled to one another; and

wherein at least two pathways of said second number of pathways of said second plurality are electrically coupled to one another.

4. The device of claim 1, further comprising a spacing material that at least spaces apart two pathways of said circuit.

5. The device of claim 4, wherein said spacing material comprises a dielectric.

6. The device of claim 1, wherein said first number of pathways of said second plurality are in a first alignment;

and

wherein said second number of pathways of said second plurality are in a second alignment.

7. The device of claim 1, wherein said first number of pathways of said second plurality are in a first superposed alignment;

and

wherein said second number of pathways of said second plurality are in a second superposed alignment.

8. The device of claim 6, wherein the first alignment and the second alignment are in a superposed alignment.

9. The device of claim 7, wherein the first and the second superposed alignment are in position at least one on top of the other.

10. The device of claim 1, wherein at least two pathways of said first number of pathways are arranged electrically coupled to one another in a first alignment;

wherein at least two pathways of said second number of pathways are arranged electrically coupled to one another in a second alignment;

wherein said first number of pathways is an odd number of pathways greater than one, and wherein said second number of pathways is an odd number of pathways greater than one; and

wherein a total number of pathways of said first plurality is at least an even number greater than two.

11. The device of claim 1, wherein at least two pathways of said first number of pathways of said second plurality are arranged in a first superposed alignment electrically coupled to 095 one another;

wherein at least two pathways of said second number of pathways of said second plurality are arranged in a second superposed alignment electrically coupled to one another;

wherein a total number of pathways of second plurality is an odd number greater than one; and

wherein a total number of pathways of said first plurality is at least an even number greater than two.

12. The device of claim 10, further comprising a spacing material that at least spaces apart pathways of said circuit arrangement.

13. The device of claim 11, wherein four pathways of the circuit arrangement are electrically isolated from one another.

14. The device of claim 1, wherein said first plurality of pathways is a plurality of shielded pathways;

and

wherein said second plurality of pathways is a plurality of shielding pathways.

32. (Currently amended) The device of claim 1 in which said device is a first level interconnect arrangement for an integrated circuit.

33. (Currently amended) The device of claim 1 in which said device is arranged as a decoupling capacitor.

34. (Currently amended) The device of claim 1 in which said device is arranged as a bypass capacitor.

35. (Currently amended) The device of claim 1 in which said device is a first level interconnect arrangement coupled to an integrated circuit;

and wherein at least said first plurality is electrically coupled to said integrated circuit.

36. (Currently amended) The device of claim 1 in which said device is a first level interconnect arrangement coupled to an integrated circuit;

wherein said first plurality is electrically coupled to said integrated circuit; and

wherein said second plurality is electrically isolated from said integrated circuit.

15. An electrical arrangement comprising:

at least a first and a second plurality of pathways;

wherein the first plurality includes at least one pair of pathways electrically isolated from each other and arranged in mutual complementary position;

wherein at least a first number of pathways of said second plurality is arranged electrically isolated from a second number of pathways of said second plurality, and wherein said second plurality includes at least two pathways electrically isolated from said first 120 plurality;

wherein at least two pathways of said first number of pathways of said second plurality are electrically coupled to one another; and

wherein at least two pathways of said second number of pathways of said second plurality are electrically coupled to one another.

16. The electrical arrangement of claim 15, further comprising a spacing material that at least spaces apart pathways of said circuit arrangement.

17. The electrical arrangement of claim 15, wherein at least four pathways of the circuit 130 arrangement are electrically isolated from one another.

18. The electrical arrangement of claim 15, wherein at least six pathways of the circuit arrangement are electrically isolated from one another.

19. The electrical arrangement of claim 15, wherein said second plurality includes at least two pathways arranged co-planar to one another;

and

wherein at least four pathways of the circuit arrangement are electrically isolated from one another.

20. The electrical arrangement of claim 15, wherein said second plurality includes at least two pathways arranged co-planar to one another;

and

wherein at least four pathways of the circuit arrangement are electrically isolated from one another.

21. The electrical arrangement of claim 15, wherein said first and said second plurality are arranged in a non co-planar stacking;

and

wherein four pathways of the circuit arrangement are electrically isolated from one another.

22. The electrical arrangement of claim 15, wherein said first plurality of pathways comprises a plurality of vias;

and

wherein said second plurality of pathways is a plurality of shielding pathways.

23. A device comprising:

at least four pluralities of pathways;

wherein only respective pathways of each one plurality of said pluralities are electrically coupled to one another; and

wherein at least two pluralities of said at least four pluralities provide shielding for at least two other pluralities of said at least four pluralities of pathways.

24. A device comprising:

at least a first, a second, a third and a four plurality of pathways;

wherein only respective pathways of each said plurality are electrically coupled to one another;

wherein said first plurality shields said second plurality; and

wherein said third plurality shields said fourth plurality.

25. A circuit arrangement comprising:

at least a first and a second plurality of shielding pathways;

at least a first and a second plurality of shielded pathways; and

wherein said shielding pathways and said shielded pathways are alternately arranged within said circuit arrangement;

wherein only respective pathways of each said plurality are electrically coupled to one another; and

wherein each of said pluralities of said circuit arrangement are electrically isolated from one another.

26. A system, comprising:

an integrated circuit package having at least one integrated circuit;

a plurality of pathways conductively coupled together;

a first plurality of shields conductively coupled together;

a second plurality of shields conductively coupled together and electrically isolated from at least said first plurality; and

wherein each of said shields and said pathways are alternately arranged, and wherein said shields develop at least one low impedance pathway suitable for energy propagation away from said integrated circuit; and

wherein said pathways develop a low inductance pathway suitable for energy propagation within said integrated circuit package, said energy propagation being conditioned 190 by at least said plurality of shields.

27. The system of claim 26, wherein said first and said second pluralities of shields are respectively in a substantially coplanar relationship.

28. The system of claim 26, wherein said first and said second pluralities of shields are respectively in a substantially coplanar relationship.

29. The system of claim 26, wherein one of said first or said second plurality of shields comprises a centering one of said shields, and wherein said first and said second pluralities of shields and said pathways are arranged in a substantially balanced and complementary symmetrical arrangement about said centering one.

30. The system of claim 26, wherein one of said first or said second plurality of shields comprises a centering one of said shields, and wherein said first and said second pluralities 205 of shields and said pathways are substantially aligned about said centering one.

31. The system of claim 26, wherein each of said first plurality and said second plurality of shields comprises an odd number of shields.

37. A device comprising:

a first electrically conductive shield layer that resides in a first plane;

a third electrically conductive shield layer that resides in a third plane;

a fifth electrically conductive shield layer that resides in a fifth plane;

said third plane is between said first plane and said fifth plane;

a first electrically conductive electrode layer that resides in a second plane, and said second plane is between said first plane and said third plane;

a third electrically conductive electrode layer that resides in a fourth plane, said fourth plane is between said third plane and said fifth plane;

said device electrically connects said first electrically conductive shield layer, said third electrically conductive shield layer, and said fifth electrically conductive shield layer to one another;

said first electrically conductive shield layer, said third electrically conductive shield layer, and said fifth electrically conductive shield layer are stacked, said first electrically conductive electrode layer is substantially between said first electrically conductive shield layer and said third electrically conductive shield layer, and said third electrically conductive electrode layer is substantially between said third electrically conductive shield layer and said fifth electrically conductive shield layer;

a second electrically conductive shield layer;

a fourth electrically conductive shield layer;

a sixth electrically conductive shield layer;

a second electrically conductive electrode layer;

a fourth electrically conductive electrode layer;

said device electrically connects said second electrically conductive shield layer, said fourth electrically conductive shield layer, and said sixth electrically conductive shield layer to one another;

said second electrically conductive shield layer, said fourth electrically conductive shield layer, and said sixth electrically conductive shield layer are stacked, said second electrically conductive electrode layer is substantially between said second electrically conductive shield layer said fourth electrically conductive shield layer, and said fourth electrically conductive electrode layer is substantially between said fourth electrically conductive shield layer and said sixth electrically conductive shield layer.

38. The device of claim 37 wherein:

said first electrically conductive shield layer and said second electrically conductive shield layer reside in a first plane;

said first electrically conductive electrode layer and said second electrically conductive electrode layer reside in a second plane, and said second plane is between said first plane and said third plane;

said third electrically conductive shield layer and said fourth electrically conductive shield layer reside in a third plane;

said fifth electrically conductive shield layer and said sixth electrically conductive shield layer reside in a fifth plane; and

said third electrically conductive electrode layer and said fourth electrically conductive electrode layer reside in a fourth plane, and said fourth plane is between said third plane and said fifth plane.

39. The device of claim 37 wherein:

said first electrically conductive shield layer, said third electrically conductive shield layer and said fifth electrically conductive shield layer are stacked upon said second electrically conductive shield layer, said fourth electrically conductive shield layer, and said sixth electrically conductive shield layer.

40. The device of claim 39 wherein:

said first electrically conductive electrode layer includes a first electrically conductive electrode layer body region and a first electrically conductive electrode layer tab region, and said first electrically conductive electrode layer tab region protrudes from said first electrically conductive electrode layer body region in a first direction in said second plane; and

said third electrically conductive electrode layer defines a third electrically conductive electrode layer body region and third electrically conductive electrode layer tab region, and said third electrically conductive electrode layer tab region protrudes from said third electrically conductive electrode layer body region in a second direction opposite said first direction.

41. The device of claim 40 wherein:

said second electrically conductive electrode layer includes a second electrically conductive electrode layer body region and a second electrically conductive electrode layer tab region, and said second electrically conductive electrode layer tab region protrudes from said second electrically conductive electrode layer body region in third direction that is perpendicular to said first direction and said second direction; and

said fourth electrically conductive electrode layer defines a fourth electrically conductive electrode layer body region and fourth electrically conductive electrode layer tab region, and said fourth electrically conductive electrode layer tab region protrudes from said fourth electrically conductive electrode layer body region in a fourth direction opposite said third direction.

42. The device of claim 37 further comprising additional electrically conductive electrode layers and additional electrically conductive shield layers.

43. The device of claim 37 further comprising an electrically conductive interconnections between two layers of said device.

44. The device of claim 37 further comprising a sixth electrically conductive shield layer adjacent said first electrically conductive shield layer, and a seventh electrically conductive shield layer adjacent said fifth electrically conductive shield layer.

45. The device of claim 37 further comprising:

a set of electrically conductive interconnections;

a set of pads protruding from a surface of said device, and

wherein each one of said set of electrically conductive interconnections connects to a different one of said set of pads.

46. The device of claim 45 wherein at least some of said set of pads are designed for connection to an integrated circuit.