Mismatched on-die termination circuits and termination methods therefor
First Claim
1. A method of terminating an external transmission line in a memory device having an on-die termination circuit, comprising:
- electrically coupling the termination circuit to the transmission line in response to a control signal which indicates that the memory device is in an active mode or a write mode;
wherein the termination circuit has an impedance value that is mismatched with an impedance value of the transmission line.
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Accused Products
Abstract
Methods of terminating an external transmission line in a memory device having an on-die termination circuit include electrically coupling the termination circuit to the transmission line in response to a control signal which indicates that the memory device is in an active mode or a write mode. The termination circuit has an impedance value that is mismatched with an impedance value of the transmission line. The termination circuit can include an input/output pad, a resistor, and a transistor connected in series to a reference voltage. Also, the termination circuit may be electrically coupled to the transmission line by activating the transistor in the termination circuit to connect the transmission line to the reference voltage in response to the control signal. Related devices are also disclosed.
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Citations
46 Claims
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1. A method of terminating an external transmission line in a memory device having an on-die termination circuit, comprising:
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electrically coupling the termination circuit to the transmission line in response to a control signal which indicates that the memory device is in an active mode or a write mode;
wherein the termination circuit has an impedance value that is mismatched with an impedance value of the transmission line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit memory device, comprising:
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a transmission line; and
a termination circuit that is electrically coupled to the transmission line responsive to a control signal which indicates that the memory device is in an active mode or a write mode;
wherein the termination circuit has an impedance value that is mismatched with an impedance value of the transmission line. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. An on-die termination circuit in a memory device, comprising:
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a pad which is connected to an external transmission line;
a resistor having two ends, one end of which is connected in series to the pad; and
an NMOS transistor connected in series between the other end of the resistor and a ground voltage, wherein the transistor has a gate connected to a termination control signal that is activated when the memory device is in an active mode or a write mode. - View Dependent Claims (20, 21, 22, 23, 24)
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25. An on-die termination circuit included in a memory device, comprising:
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a pad which is connected to an external transmission line;
a resistor having two ends, one end of which is connected in series to the pad; and
a PMOS transistor connected in series between the other end of the resistor and a voltage source, wherein the transistor has a gate connected to a termination control signal that is activated when the memory device is in an active mode or a write mode. - View Dependent Claims (26, 27, 28, 29, 30)
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31. An on-die termination circuit in a memory device, comprising:
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a DQ pad, a DQS pad, and a DM pad, each of which is respectively connected to external transmission lines;
resistors having two ends, one ends of which are connected in series to the pads, respectively; and
NMOS transistors connected in series between the other ends of the resistors and a ground voltage, wherein the transistors have gates connected to termination control signals that are activated when the memory device is in an active mode or a write mode, wherein a sum of a resistance value of each resistor and an on-resistance value of each NMOS transistor is mismatched with an impedance value of each transmission line. - View Dependent Claims (32, 33)
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34. An on-die termination circuit in a memory device, comprising:
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a DQ pad, a DQS pad, and a DM pad, each of which is connected to transmission lines provided from the external;
resistors having two ends, one ends of which are connected in series to the pads, respectively; and
PMOS transistors connected in series between the other ends of the resistors and a source voltage, wherein the transistors have gates connected to termination control signals that are activated when the memory device is in an active mode or write mode, wherein a sum of a resistance value of each resistor and an on-resistance value of each PMOS transistor is mismatched with an impedance value of each transmission line. - View Dependent Claims (35, 36)
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37. A method for terminating a transmission line connected to a pad of a memory device, the method comprising:
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activating a termination control signal in response to an active mode or a write mode of the memory device;
turning on an NMOS transistor in response to the termination control signal; and
electrically coupling the pad to a ground voltage through a serially connected resistor and the NMOS transistor, wherein a sum of a resistance value of the resistor and an on-resistance value of the NMOS transistor is mismatched with an impedance value of the transmission line. - View Dependent Claims (38, 39, 40, 41)
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42. A method for terminating a transmission line connected to a pad of a memory device, the method comprising:
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activating a termination control signal in response to an active mode or a write mode of the memory device;
turning on a PMOS transistor in response to the termination control signal; and
electrically coupling the pad to a source voltage through a serially connected resistor and the PMOS transistor, wherein a sum of a resistance value of the resistor and an on-resistance value of the PMOS transistor is mismatched with an impedance value of the transmission line. - View Dependent Claims (43, 44, 45, 46)
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Specification