[LOW TEMPERATURE POLYSILICON THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME]

• US 20040219723A1
• Filed: 08/07/2003
• Published: 11/04/2004
• Est. Priority Date: 04/16/2003
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Sun, Ming-Wei, Peng, Chia-Tien
• Granted Patent: US 7,335,540 B2
• Time in Patent Office: Days
• US Class Current: 438/166
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A low temperature polysilicon thin film transistor and method of manufacturing the same is provided. The low temperature polysilicon thin film transistor comprises a channel region. Among others, one feature of the method according to the present invention is the performance of a plasma treatment to adjust the threshold voltage of the low temperature polysilicon thin film transistor. Because the threshold voltage of the low temperature polysilicon thin film transistor can be adjusted through a plasma treatment, the manufacturing process is more flexible.

Claims

1. A method of forming a low temperature polysilicon thin film transistor, comprising the steps of:

forming an amorphous silicon layer over a substrate;

performing a plasma treatment;

transforming the amorphous silicon layer into a polysilicon layer;

patterning the polysilicon layer to form a plurality of island polysilicon layers;

forming a channel region and a doped source/drain region on each side of the channel region in each island polysilicon layer; and

forming a gate over each channel region.

2. The method of claim 1, wherein the step of performing the plasma treatment comprises applying an oxygen-containing plasma to adjust the threshold voltage in the negative direction.

3. The method of claim 2, wherein the oxygen-containing plasma comprises nitrous oxide (N₂O) plasma.

4. The method of claim 1, wherein the step of performing the plasma treatment comprises applying a hydrogen-containing plasma to adjust the threshold voltage in the positive direction.

5. The method of claim 4, wherein the hydrogen-containing plasma comprises ammonia (NH₃) plasma.

6. The method of claim 4, wherein the hydrogen-containing plasma comprises hydrogen (H₂) plasma.

7. The method of claim 1, wherein the desired shift in the threshold voltage is effected by varying the radio frequency power to the plasma treatment.

8. The method of claim 1, wherein the desired shift in the threshold voltage is effected by varying the processing period of the plasma treatment.

9. The method of claim 1, wherein the step of patterning the polysilicon layer further comprises forming a gate insulation layer over the island polysilicon layers.

10. A method of forming a low temperature polysilicon thin film transistor, comprising the steps of:

providing a substrate;

forming an amorphous silicon layer over the substrate;

performing a plasma treatment;

performing a laser annealing process to transform the amorphous silicon layer into a polysilicon layer;

patterning the polysilicon layer to form a plurality of island polysilicon layers;

forming a gate insulation layer over the island polysilicon layers;

forming a channel region in each island polysilicon layer and a doped source/drain region on each side to the channel regions; and

forming a gate over the channel regions.

11. The method of claim 10, wherein the step of performing the plasma treatment comprises applying an oxygen-containing plasma to adjust the threshold voltage in the negative direction.

12. The method of claim 11, wherein the oxygen-containing plasma comprises nitrous oxide (N₂O) plasma.

13. The method of claim 10, wherein the step of performing the plasma treatment comprises applying a hydrogen-containing plasma to adjust the threshold voltage in the positive direction.

14. The method of claim 13, wherein the hydrogen-containing plasma comprises ammonia (NH₃) plasma.

15. The method of claim 13, wherein the hydrogen-containing plasma comprises hydrogen (H₂) plasma.

16. The method of claim 10, wherein the desired shift in the threshold voltage is effected by varying the radio frequency power to the plasma treatment.

17. The method of claim 10, wherein the desired shift in the threshold voltage is effected by varying the processing period of the plasma treatment.

18. The method of claim 10, wherein the laser annealing process comprises performing an excimer laser annealing process.

19. The method of claim 10, wherein the step of forming the amorphous silicon layer over the substrate, further comprises:

forming a silicon nitride layer over the substrate; and

forming a silicon oxide layer over the silicon nitride layer.

20. The method of claim 10, wherein the step of forming a channel layer in each island polysilicon layer and a doped source/drain region on each side to the channel region further comprises:

forming a first patterned photoresist layer over the gate insulation layer to expose the upper surface of on each side of each island polysilicon layer; and

performing a p⁺ doping process.

21. The method of claim 20, wherein the step of performing the p⁺ doping process further comprises removing the first patterned photoresist layer.

22. The method of claim 10, wherein the step of forming a channel region in each island polysilicon layer and a doped source/drain region on each side to the channel region further comprises:

forming a second patterned photoresist layer over the substrate to cover a portion of the various island polysilicon layers and expose the upper surface on each side of the island polysilicon layers; and

performing an n⁺ doping process.

23. The method of claim 22, wherein the step of performing the n⁺ doping process further comprises removing the second patterned photoresist layer.

24. The method of claim 23, wherein the step of removing the second patterned photoresist layer further comprises:

forming a third patterned photoresist layer over the gate insulation layer to expose an area adjacent to the doped source/drain region of various island polysilicon layer; and

performing an n⁺ doping process to form lightly doped drain regions.

25. The method of claim 24, wherein the step of performing the n⁻

doping process further comprises removing the third patterned photoresist layer.

26. The method of claim 10, wherein the step of forming a gate over the channel regions further comprises performing an activation process.

27. The method of claim 10, wherein the step of forming a gate over the channel regions further comprises:

forming an inter-layer dielectric over the substrate;

forming a plurality of first openings in the inter-layer dielectric and the gate insulation layer to expose the doped source/drain regions; and

forming a plurality of source/drain metallic contacts over the inter-layer dielectric so that the source/drain metallic contacts and various doped source/drain regions are electrically connected via the first openings.

28. The method of claim 27, wherein the step of forming a plurality of source/drain metallic contacts further comprises:

forming a passivation layer over the substrate;

forming a second opening in the passivation layer to expose a portion of the source/drain metallic contact; and

forming a pixel electrode over the passivation layer such that the pixel electrode and a portion of the source/drain metallic contact are electrically connected through the second opening.

29. A low temperature polysilicon thin film transistor, comprising a polysilicon layer, a gate and a gate insulation layer, wherein the gate insulation layer is positioned between the gate and the polysilicon layer, the polysilicon layer has a channel region, and the concentration of oxygen within the channel region is between 1E19 to 1E23 atoms/cc while the concentration of hydrogen within the channel region is between 5E16 to 1E19 atoms/cc.

30. The low temperature polysilicon thin film transistor of claim 29, wherein the transistor further comprises a plurality of doped source/drain regions positioned in the polysilicon layer on each side to the channel region.

31. The low temperature polysilicon thin film transistor of claim 30, wherein the doped source/drain regions comprise p-doped regions.

32. The low temperature polysilicon thin film transistor of claim 30, wherein the doped source/drain regions comprise n-doped regions.

33. The low temperature polysilicon thin film transistor of claim 32, wherein the transistor further comprises a lightly doped drain region positioned between the doped source/drain region and the channel region.

34. The low temperature polysilicon thin film transistor of claim 30, wherein the transistor further comprises an inter-layer dielectric positioned over the gate insulation layer with the inter-layer dielectric having a plurality of first openings that exposes the doped source/drain regions.

35. The low temperature polysilicon thin film transistor of claim 34, wherein the transistor further comprises a plurality of source/drain metallic contacts for connecting electrically with the doped source/drain regions via the first openings.

36. The low temperature polysilicon thin film transistor of claim 35, wherein the transistor further comprises a passivation layer positioned to cover the inter-layer dielectric and the source/drain metallic contacts such that the passivation layer has a second opening that exposes a portion of the source/drain metallic contact.

37. The low temperature polysilicon thin film transistor of claim 36, wherein the passivation layer comprises a silicon nitride layer.

38. The low temperature polysilicon thin film transistor of claim 36, wherein the transistor further comprises a pixel electrode positioned over the passivation layer and electrically connected to a portion of the source/drain metallic contact via the second opening.

39. The low temperature polysilicon thin film transistor of claim 38, wherein material constituting the pixel electrode comprises indium-tin oxide.