Automated analysis of RTL code containing ASIC vendor rules

• US 20040221249A1
• Filed: 04/30/2003
• Published: 11/04/2004
• Est. Priority Date: 04/30/2003
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Balasubramanian, Balamurugan, Chaturvedula, Kavitha, Fry, Randall P., Lahner, Juergen, Adusumalli, Srinivas, Atmakuri, Kiran, Devineni, Krishna, Pierce, Gregory A.
• Granted Patent: US 7,082,584 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method of automatically analyzing RTL code includes steps for receiving as input RTL code for an integrated circuit design, selecting an RTL platform incorporating circuit design rules for a vendor of the integrated circuit design, displaying the design rules from the RTL platform on a graphic user interface, selecting a number of the design rules from the graphic user interface, performing an analysis in the RTL platform of the RTL code for each of the selected design rules, and generating as output a result of the analysis for each of the selected design rules.

Claims

1. A method of automatically analyzing RTL code comprising steps for:

(a) receiving as input RTL code for an integrated circuit design;

(b) selecting an RTL platform incorporating design rules for a vendor of the integrated circuit design;

(c) displaying the design rules from the RTL platform on a graphic user interface;

(d) selecting a number of the design rules from the graphic user interface;

(e) performing an analysis in the RTL platform of the RTL code for each of the selected design rules; and

(f) generating as output a result of the analysis for each of the selected design rules.

2. The method of claim 1 wherein step (d) further includes selecting an option to enable or disable a rule from the graphic user interface.

3. The method of claim 1 wherein step (d) further includes selecting a threshold value for a rule from the graphic user interface.

4. The method of claim 1 wherein step (d) further includes selecting a severity level for a rule from the graphic user interface.

5. The method of claim 1 wherein the design rules include detecting and identifying a possible RTL coding problem consisting of at least one of missing clock information, unconstrained I/O, critical paths, time budgeting, large structures, local congestion, unused ports, floating pins, global congestion, latches, unregistered I/O, high fanout nets, shift registers, logic depth, clock domain crossings, gate explosion, resource sharing, use of casex/casez, incomplete case statements, critical multiplexer structures, gated reset, asynchronous/combinational loops, multiple driven nets, logical cone fanin, logical cone fanout, and large arithmetic operators.

6. The method of claim 1 further comprising a step of generating a cross-probing display including a logical hierarchy window, a timing analysis window, a layout window, a schematic window, and an RTL code window.

7. A computer program product for automatically analyzing RTL code comprising:

a medium for embodying a computer program for input to a computer; and

a computer program embodied in the medium for causing the computer to perform the following functions;

(a) receiving as input RTL code for an integrated circuit design;

(b) selecting an RTL platform incorporating design rules for a vendor of the integrated circuit design;

(c) displaying the design rules from the RTL platform on a graphic user interface;

(d) selecting a number of the design rules from the graphic user interface;

(e) performing an analysis in the RTL platform of the RTL code for each of the selected design rules; and

(f) generating as output a result of the analysis for each of the selected design rules.

8. The computer program product of claim 7 wherein function (d) further includes selecting an option to enable or disable a rule from the graphic user interface.

9. The computer program product of claim 7 wherein function (d) further includes selecting a threshold value for a rule from the graphic user interface.

10. The computer program product of claim 7 wherein function (d) further includes selecting a severity level for a rule from the graphic user interface.

11. The computer program product of claim 7 wherein the design rules include detecting and identifying a possible RTL coding problem consisting of at least one of missing clock information, unconstrained I/O, critical paths, time budgeting, large structures, local congestion, unused ports, floating pins, global congestion, latches, unregistered I/O, high fanout nets, shift registers, logic depth, clock domain crossings, gate explosion, resource sharing, use of casex/casez, incomplete case statements, critical multiplexer structures, gated reset, asynchronous/combinational loops, multiple driven nets, logical cone fanin, logical cone fanout, and large arithmetic operators.

12. The computer program product of claim 7 further comprising generating a cross-probing display including a logical hierarchy window, a timing analysis window, a layout window, a schematic window, and an RTL code window.