CMOS inverter layout
First Claim
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1. CMOS inverter, comprising:
- a. a first transistor comprising a first gate, a first drain, and a first source; and
b. a second transistor comprising a second gate, a second drain, and a second source, the second transistor disposed proximate the first transistor;
c. an input for an inverter, comprising a generally Z-shaped first connector operatively connecting the first gate and the second gate; and
d. an output for the inverter, comprising a second connector operatively connecting the first drain and the second drain.
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Abstract
A CMOS circuit such as an inverter or latch is disclosed where transistors used in the circuit are interconnected using a connector disposed intermediate, and operatively connecting, a gate of a first transistor forming region and a gate of a second transistor forming region, the connector generally defining a Z-shape. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
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Citations
8 Claims
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1. CMOS inverter, comprising:
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a. a first transistor comprising a first gate, a first drain, and a first source; and
b. a second transistor comprising a second gate, a second drain, and a second source, the second transistor disposed proximate the first transistor;
c. an input for an inverter, comprising a generally Z-shaped first connector operatively connecting the first gate and the second gate; and
d. an output for the inverter, comprising a second connector operatively connecting the first drain and the second drain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification