CMOS inverter layout

• US 20040222422A1
• Filed: 05/08/2003
• Published: 11/11/2004
• Est. Priority Date: 05/08/2003
• Status: Abandoned Application

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Jen-Yi, Hu, Sun, Wein-Town
• Application Number:
  US10/434,296
• Publication Number:
  US 20040222422A1
• Time in Patent Office: Days
• US Class Current: 257/69
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A CMOS circuit such as an inverter or latch is disclosed where transistors used in the circuit are interconnected using a connector disposed intermediate, and operatively connecting, a gate of a first transistor forming region and a gate of a second transistor forming region, the connector generally defining a Z-shape. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. CMOS inverter, comprising:

a. a first transistor comprising a first gate, a first drain, and a first source; and

b. a second transistor comprising a second gate, a second drain, and a second source, the second transistor disposed proximate the first transistor;

c. an input for an inverter, comprising a generally Z-shaped first connector operatively connecting the first gate and the second gate; and

d. an output for the inverter, comprising a second connector operatively connecting the first drain and the second drain.

2. The CMOS inverter of claim 1, wherein:

a. at least one of the first transistor or the second transistor is a thin film transistor.

3. The CMOS inverter of claim 1, wherein:

a. the first transistor is fabricated in a first transistor forming region on a semiconductor substrate of a first conductivity type region of the semiconductor substrate, the first transistor forming region comprising;

i. a first rectilinear portion extending in a first direction;

ii. a drain region defined in the first rectilinear portion;

iii. a gate region defined in the first rectilinear portion; and

iv. a source region defined in the first rectilinear portion;

b. the second transistor is fabricated in a second transistor forming region on the semiconductor substrate of a second conductivity type region of the semiconductor substrate, the second transistor forming region comprising;

i. a second rectilinear portion extending in a direction substantially parallel to the first rectilinear portion in the first direction;

ii. a drain region defined in the second rectilinear portion;

iii. a gate region defined in the second rectilinear portion; and

iv. a source region defined in the second rectilinear portion; and

c. the first connector further comprises;

i. a first connector leg operatively connected to the first gate and disposed substantially perpendicular to the first transistor forming region;

ii. a second connector leg operatively connected to the second gate and disposed substantially perpendicular to the second transistor forming region; and

iii. a third connector leg operatively connected to the first connector leg and the second connector leg and disposed substantially parallel to the first transistor forming region and the second transistor forming region;

d. wherein a first predetermined portion of the first connector leg is disposed on a side of the third connector leg and a second predetermined portion of the second connector leg is disposed on an opposite side of the third connector leg.

4. The CMOS inverter of claim 3, wherein:

a. the first transistor forming region defines at least one of (i) an n-type transistor or (ii) a p-type transistor; and

b. the second transistor forming region defines a transistor of a type opposite the first transistor.

5. The CMOS inverter of claim 3, wherein:

a. the first transistor forming region and the second transistor forming region are fabricated side by side onto a substrate; and

b. the first gate substantially overlaps the second gate.

6. The CMOS inverter of claim 1, wherein:

a. a width of a circuit comprising the first transistor, the second transistor, a voltage source V_DD, and a voltage source V_SS is around 28 μ

m for first transistor and second transistor widths of around 6 μ

m.

7. The CMOS inverter of claim 1, wherein:

a. the CMOS inverter is fabricated using at least one of (i) a low-temperature polysilicon (LTPS) transistor (TFT) fabrication technique or (ii) a polymer (organic) TFT fabrication technique.

8. The CMOS inverter of claim 7, wherein:

a. the CMOS inverter is fabricated on at least one of (i) a glass substrate or (ii) a plastic substrate.