HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION
First Claim
1. A transistor comprising:
- a gate oxide on a substrate;
a gate on said gate oxide;
a channel region in said substrate below said gate;
a source region in said substrate on one side of said channel region;
a drain region in said substrate on an opposite side of said channel region from said source region;
a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and
a drain extension below said STI region, wherein said drain extension is separated from said gate oxide.
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Abstract
A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.
30 Citations
14 Claims
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1. A transistor comprising:
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a gate oxide on a substrate;
a gate on said gate oxide;
a channel region in said substrate below said gate;
a source region in said substrate on one side of said channel region;
a drain region in said substrate on an opposite side of said channel region from said source region;
a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and
a drain extension below said STI region, wherein said drain extension is separated from said gate oxide. - View Dependent Claims (2, 5, 6, 7)
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3. A transistor comprising:
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a gate on a substrate;
a channel region in said substrate below said gate;
a source region in said substrate on one side of said channel region;
a drain region in said substrate on an opposite side of said channel region from said source region;
a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and
a drain extension below said STI region;
wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region, wherein portions of said drain extension along said bottom of said STI region comprise different dopant implants than said portions of said drain extensions along said sides of said STI region.
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4. A transistor comprising:
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a gate on a substrate;
a channel region in said substrate below said gate;
a source region in said substrate on one side of said channel region;
a drain region in said substrate on an opposite side of said channel region from said source region;
a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and
a drain extension below said STI region;
wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region, wherein portions of said drain extensions along sides of said STI region extend from said bottom of said STI region to a position partially up said sides of said STI region.
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8. A transistor comprising:
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a gate oxide on a substrate;
a gate on said gate oxide;
a channel region in said substrate below said gate;
a source region in said substrate on one side of said channel region;
a drain region in said substrate on an opposite side of said channel region from said source region;
a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and
a drain extension below said STI region, wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region, and said drain extension is separated from said gate oxide. - View Dependent Claims (11, 12, 13)
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9. A transistor comprising:
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a gate on a substrate;
a channel region in said substrate below said gate;
a source region in said substrate on one side of said channel region;
a drain region in said substrate on an opposite side of said channel region from said source region;
a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and
a drain extension below said STI region wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region, wherein portions of said drain extension along said bottom of said STI region comprise different dopant implants than said portions of said drain extensions along said sides of said STI region.
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10. A transistor comprising:
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a gate on a substrate;
a channel region in said substrate below said gate;
a source region in said substrate on one side of said channel region;
a drain region in said substrate on an opposite side of said channel region from said source region;
a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and
a drain extension below said STI region, wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region, wherein portions of said drain extension along said bottom of said STI region comprise different dopant implants than said portions of said drain extensions along said sides of said STI region, wherein portions of said drain extensions along sides of said STI region extend from said bottom of said STI region to a position partially up said sides of said STI region.
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14-20. -20. (Canceled).
Specification