Integrated circuit package configuration incorporating shielded circuit element structure

• US 20040222506A1
• Filed: 06/18/2003
• Published: 11/11/2004
• Est. Priority Date: 10/15/2002
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Thomsen, Axel, Shi, Ying, Smith, Kevin G., Wei, Derrick C., Pietruszynski, David M., Proffitt, Steven P.
• Granted Patent: US 7,141,883 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01F 2017/008 Electric or magnetic shielding of printed inductances
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formed around the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.

Claims

1. An apparatus comprising:

a multi-layer package substrate;

an integrated circuit die attached by solder bumps to the multi-layer package substrate;

an LC oscillator circuit formed largely within the integrated circuit die, having an LC tank circuit including at least one inductor formed within the multi-layer package substrate; and

an electromagnetic shielding structure formed around the at least one inductor.

2. The apparatus as recited in claim 1 wherein the shielding structure comprises an electrically conductive enclosure formed substantially around the at least one inductor.

3. The apparatus as recited in claim 2 wherein the shielding structure comprises an electrically conductive enclosure having a top plate, a bottom plate, and sidewalls, formed at least in part by various layers of the multi-layer package substrate.

4. The apparatus as recited in claim 3 wherein at least one of the top plate or bottom plate of the shielding structure is formed by a conductive layer of the integrated circuit die once attached to the multi-layer package substrate.

5. The apparatus as recited in claim 3 wherein both the top plate and the bottom plate of the shielding structure are formed by a respective conductive layer of the multi-layer package substrate.

6. The apparatus as recited in claim 3 wherein the sidewalls of the shielding structure are formed by a ring of stacked via structures in at least the multi-layer package substrate.

7. The apparatus as recited in claim 3 wherein the sidewalls of the shielding structure are formed by a ring of stacked via structures in both the integrated circuit die and the multi-layer package substrate.

8. The apparatus as recited in claim 7 wherein the stacked via structures in the integrated circuit die are connected to the stacked via structures in the multi-layer package substrate by solder bumps.

9. The apparatus as recited in claim 3 wherein the sidewalls of the shielding structure are formed by a substantially solid plate formed around the perimeter of the shielding structure in at least the multi-layer package substrate.

10. The apparatus as recited in claim 1 wherein the LC oscillator circuit forms a portion a phase locked loop (PLL) circuit.

11. The apparatus as recited in claim 10 wherein the PLL circuit forms a portion of a clock generation circuit.

12. The apparatus as recited in claim 10 wherein the PLL circuit forms a portion of a clock and data recovery circuit.

13. An apparatus comprising:

a multi-layer package substrate;

at least one inductor formed on a layer of the multi-layer package substrate;

an electromagnetic shielding structure formed around the inductor; and

a plurality of conductive pads for attaching an integrated circuit die to the multi-layer package substrate and for connecting the at least one inductor to the integrated circuit die.

14. The apparatus as recited in claim 13 further comprising conductive pads for connecting the electromagnetic shielding structure to the integrated circuit die.

15. The apparatus as recited in claim 13 wherein the shielding structure comprises an electrically conductive enclosure formed substantially around the at least one inductor.

16. The apparatus as recited in claim 13 wherein the shielding structure comprises an electrically conductive enclosure having at least a top plate and sidewalls formed by various layers of the multi-layer package substrate.

17. The apparatus as recited in claim 16 wherein at least one of the top plate or bottom plate of the shielding structure is formed by a conductive layer of an integrated circuit die once attached to the multi-layer package substrate.

18. The apparatus as recited in claim 16 wherein both the top plate and the bottom plate of the magnetic shielding structure are formed by a respective conductive layer of the multi-layer package substrate.

19. The apparatus as recited in claim 16 wherein the sidewalls of the shielding structure are formed by a ring of stacked via structures in the multi-layer package substrate.

20. The apparatus as recited in claim 16 wherein the stacked via structures in the multi-layer package substrate include metal pads for connection of the sidewall by solder bumps to the integrated circuit die.

21. The apparatus as recited in claim 16 wherein the sidewalls of the shielding structure are formed by a substantially solid plate formed around the perimeter of the shielding structure.

22. An apparatus comprising:

a multi-layer package substrate;

an integrated circuit die attached to the multi-layer package substrate;

at least one circuit element formed within the multi-layer packaging substrate and closely coupled to remaining circuitry within the integrated circuit die; and

an electromagnetic shielding structure formed around the at least one circuit element.

23. The apparatus as recited in claim 22 wherein the electromagnetic shielding structure comprises an electrically conductive enclosure having a top plate, a bottom plate, and sidewalls, formed at least in part by various layers of the multi-layer package substrate.

24. The apparatus as recited in claim 23 wherein at least one of the top plate or bottom plate of the electromagnetic shielding structure is formed by a conductive layer formed on the integrated circuit die attached to the multi-layer package substrate.

25. The apparatus as recited in claim 23 wherein both the top plate and the bottom plate of the electromagnetic shielding structure are formed by a respective conductive layer of the multi-layer package substrate.

26. The apparatus as recited in claim 23 wherein the sidewalls of the electromagnetic shielding structure are formed by a ring of stacked via structures in at least the multi-layer package substrate.

27. The apparatus as recited in claim 23 wherein the sidewalls of the electromagnetic shielding structure are formed by a ring of stacked via structures in both the integrated circuit die and the multi-layer package substrate.

28. The apparatus as recited in claim 27 wherein the stacked via structures forming the sidewall in the integrated circuit die are connected by solder bumps to the stacked via structures forming the sidewall in the multi-layer package substrate.

29. The apparatus as recited in claim 23 wherein the sidewalls of the electromagnetic shielding structure are formed by a substantially solid plate formed around the perimeter of the shielding structure in at least the multi-layer package substrate.

30. The apparatus as recited in claim 22 wherein the at least one circuit element comprises an inductor structure.

31. The apparatus as recited in claim 30 wherein the inductor structure comprises a parallel-connected pair of inductor loops forming a magnetic dipole.

32. The apparatus as recited in claim 30 wherein the inductor structure comprises a series-connected pair of inductor loops.

33. The apparatus as recited in claim 22 wherein the at least one circuit element comprises a capacitance structure.

34. A computer-readable medium encoding a multi-layer package substrate for attaching an integrated circuit die thereto, said encoded multi-layer package substrate comprising:

at least one circuit element formed on one or more layers of the multi-layer packaging substrate;

an electromagnetic shielding structure formed around the at least one circuit element; and

metal pads for attaching an integrated circuit die to the multi-layer package substrate and for connecting the at least one circuit element to the integrated circuit die.

35. The computer-readable medium as recited in claim 34 wherein the electromagnetic shielding structure comprises an electrically conductive enclosure having at least a top or bottom plate and having sidewalls, formed at least in part by various layers of the multi-layer package substrate.

36. The computer-readable medium as recited in claim 35 wherein at least one of the top plate or bottom plate of the electromagnetic shielding structure is formed by a conductive layer on an integrated circuit die once attached to the multi-layer package substrate.

37. The computer-readable medium as recited in claim 35 wherein both the top plate and the bottom plate of the electromagnetic shielding structure are formed by a respective conductive layer of the multi-layer package substrate.

38. The computer-readable medium as recited in claim 35 further comprising metal pads for connecting the sidewall in the multi-layer package substrate to corresponding sidewall structures of an integrated circuit die, using solder bumps.

39. The computer-readable medium as recited in claim 35 wherein the sidewalls of the electromagnetic shielding structure are formed by a ring of stacked via structures in the multi-layer package substrate.

40. The computer-readable medium as recited in claim 35 wherein the sidewalls of the electromagnetic shielding structure are formed by a substantially solid plate formed around the perimeter of the shielding structure in the multi-layer package substrate.

41. The computer-readable medium as recited in claim 34 wherein the at least one circuit element comprises an inductor structure.

42. The computer-readable medium as recited in claim 41 wherein the inductor structure comprises a parallel-connected pair of inductor loops forming a magnetic dipole.

43. The computer-readable medium as recited in claim 34 wherein the at least one circuit element comprises a capacitance structure.

44. A method of manufacturing a packaged integrated circuit product comprising the steps of:

providing a multi-layer package substrate having at least one inductor formed on a layer of the multi-layer package substrate and further having an electromagnetic shielding structure formed around the at least one inductor; and

attaching an integrated circuit die to the multi-layer package substrate using solder bumps;

wherein the at least one inductor is coupled to remaining circuitry within the integrated circuit die by one or more solder bumps.

45. The method as recited in claim 44 wherein the integrated circuit die comprises an LC oscillator circuit formed largely within the integrated circuit die, having an LC tank circuit including the at least one inductor formed within the multi-layer package substrate.

46. The method as recited in claim 45 wherein the LC oscillator circuit forms a portion a phase locked loop (PLL) circuit.

47. The method as recited in claim 46 wherein the PLL circuit forms a portion of a clock generation circuit.

48. The method as recited in claim 46 wherein the PLL circuit forms a portion of a clock and data recovery circuit.