Parallel pipelined merge engines
First Claim
1. A system for generating images comprising:
- a pixel bus;
a host bus;
a plurality of merge engines, each merge engine comprising;
a pixel bus interface circuit configured to send and receive pixel data and control messages over the pixel bus between merge engines;
a part image bus configured to communicate with a render engine associated the merge engine; and
a host interface configured to send and receive pixel data and control messages over the host bus between the merge engine and a host system.
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Abstract
An image generator is organized into a plurality of rendering engines, each of which renders an image of a part scene and provides the part image to a merge engine associated with that rendering engine. The image is a part image in that it usually contains less than all of the objects in the image to be rendered. The merge engine merges the part image from its associated rendering engine with the part image provided by a prior merge engine and provides the merged part image to a next merge engine. One or more merge engines are designated the output merge engines and these output merge engines output a merged part image that is (a portion of) the ultimate output of the image generator, the full rendered image. Each merge engine performs its merge process on the pixels it has from its rendering engine and from its prior neighbor merge engine, in a pipelined manner and without necessarily waiting for all of the pixels of the part image or the merged part image.
173 Citations
38 Claims
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1. A system for generating images comprising:
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a pixel bus;
a host bus;
a plurality of merge engines, each merge engine comprising;
a pixel bus interface circuit configured to send and receive pixel data and control messages over the pixel bus between merge engines;
a part image bus configured to communicate with a render engine associated the merge engine; and
a host interface configured to send and receive pixel data and control messages over the host bus between the merge engine and a host system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A graphics merge engine comprising:
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a pixel bus interface circuit configured to send and receive pixel data and control messages over a pixel bus between merge engines;
a part image bus configured to communicate with a render engine associated the merge engine;
a host interface configured to send and receive pixel data and control messages over a host bus between the merge engine and a host system; and
a pixel data compare circuit in communication with the pixel bus interface, part image bus, and host interface. - View Dependent Claims (10, 11, 12)
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13. A graphics processing system comprising:
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a host processor;
a rendering engine;
a graphics memory in communication with the rendering engine;
a merge processor in communication with the graphics memory, the merge processor comprising;
a pixel bus interface circuit configured to send and receive pixel data and control messages over the pixel bus between other merge processors and workstations;
a host interface configured to send and receive pixel data and control messages over the host bus between the merge processor and the host processor; and
a pixel merge circuit. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A graphics processing system comprising:
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a pixel bus for communicating data comprising pixel information;
a plurality of merge processors for merging pixel information received from at least one neighbor processor;
a plurality of rendering processors in communication with at least one merge processor and for rendering pixel information; and
a switch network for assigning and reassigning which processors are input neighbors and which processors are output neighbors. - View Dependent Claims (22, 23)
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24. A graphics processing system comprising:
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a pixel bus for communicating data comprising pixel information;
a plurality of merge processors for merging pixel information received from at least one neighbor processor, the plurality of merge processors forming a first state of input neighbor and output neighbor associations for a first image and a second state of input neighbor and output neighbor associations for a second image;
a plurality of rendering processors in communication with at least one merge processor and for rendering pixel information; and
a switch network for changing between the first state of input neighbor and output neighbor associations for the first image and the second state of input neighbor and output neighbor associations for the second image. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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31. A system for generating images comprising:
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a plurality of merge engines comprising at least one merge engine having a plurality of configuration registers that identify a plurality of operating modes of the merge engine;
a host in communication with at least the at least one merge engine and arranged to write data to the configuration registers to configure the merge engine to operate in at least a first mode of image analysis. - View Dependent Claims (32, 33, 34, 35)
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36. A network comprising:
a plurality of workstations in communication with each other, at least one work station comprising;
a memory;
an image rendering engine;
an image merge engine in communication with the rendering engine and comprising;
an input neighbor merge engine data bus;
an output neighbor merge engine data bus; and
a plurality of registers that define a first state of input neighbor merge engine and output neighbor merge engine associations and wherein the plurality of registers are modifiable to define a second state of input neighbor merge engine and output neighbor merge engine associations different from the first. - View Dependent Claims (37, 38)
Specification