NAND flash memory with improved read and verification threshold uniformity
First Claim
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1. A method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising:
- determining a position of a first accessed cell, of a plurality of cells in a series configuration, with reference to a ground potential in the flash memory device; and
adjusting a first word line signal voltage level, coupled to the first accessed cell, in response to the position of the first accessed cell.
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Abstract
A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is determined with reference to a ground potential in the flash memory device. A first word line signal is coupled to the first accessed cell. The first word line signal voltage level is adjusted in response to the position of the first accessed cell in its series of cells.
83 Citations
27 Claims
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1. A method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising:
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determining a position of a first accessed cell, of a plurality of cells in a series configuration, with reference to a ground potential in the flash memory device; and
adjusting a first word line signal voltage level, coupled to the first accessed cell, in response to the position of the first accessed cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for increasing read and erase verification threshold uniformity in a NAND flash memory device, the method comprising:
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determining a position of a first accessed cell, of a plurality of cells in a series configuration, with reference to a ground potential in the flash memory device;
generating a word line signal having a first voltage level in response to an address input; and
compensating the first voltage level in response to the position of the first accessed cell. - View Dependent Claims (11, 12)
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13. A flash memory device comprising:
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a memory array comprising a plurality of memory cells coupled together in a series configuration, a first end of the series configuration coupled to a bit line and a second end of the series configuration coupled to a ground potential reference;
a column decoder that generates the bit line;
a row decoder that generates a word line having a nominal voltage level; and
a voltage generator circuit, coupled between the row decoder and the memory array, that adjusts the nominal voltage level in response to the position of a first memory cell indicated by the word line. - View Dependent Claims (14, 15, 16)
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17. A NAND flash memory device comprising:
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a memory array comprising a plurality of memory cells coupled together in a plurality of series configurations, one end of each series configuration coupled to a bit line of a plurality of bit lines and an opposite end of each series configuration coupled to a ground potential reference;
a column decoder coupled to the memory array that generates the plurality of bit lines;
a row decoder that generates a plurality of word lines each having a nominal voltage level, a first word line capable of accessing a first cell in a first series configuration; and
a voltage generator circuit, coupled between the row decoder and the memory array, that generates a predetermined voltage level on the first word line in response to a position of the first cell in the first series configuration.
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18. A method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising:
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reading a first cell of a plurality of cells coupled together in a series configuration;
determining a position of the first cell with reference to a ground potential in the flash memory device; and
generating a reference current in response to the position. - View Dependent Claims (19, 20, 22)
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21. A method for increasing read and erase verification threshold uniformity in a flash memory device, the method comprising:
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reading a first cell of a plurality of cells coupled together in a series configuration;
determining a position of the first cell with reference to a ground potential in the flash memory device; and
generating a reference voltage in response to the position.
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23. A method for increasing read and erase verification threshold uniformity in a NAND flash memory device, the method comprising:
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reading a first cell of a plurality of cells, coupled together in a series configuration, in response to an address;
decoding the address to determine a position of the first cell with reference to a ground potential in the flash memory device;
generating a reference current in response to the position; and
comparing the reference current to a measured current of the first cell.
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24. A method for increasing read and erase verification threshold uniformity in a NAND flash memory device, the method comprising:
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reading a first cell of a plurality of cells, coupled together in a series configuration, in response to an address;
decoding the address to determine a position of the first cell with reference to a ground potential in the flash memory device;
generating a reference voltage in response to the position; and
comparing the reference voltage to a measured voltage of the first cell.
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25. A flash memory device comprising:
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a memory array comprising a plurality of cells coupled together in a plurality of series configurations; and
a reference generator that generates a measurement reference for each of the plurality of cells based on their locations in each of the plurality of series configurations. - View Dependent Claims (26, 27)
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Specification