System and method for compensating for skew between a first clock signal and a second clock signal
First Claim
1. A system for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧
- 1, comprising;
a phase detector operable to detect a phase between said first clock signal and said second clock signal;
a skew state detector disposed in communication with said phase detector for generating a skew state signal which tracks a phase relationship between said first clock signal and said second clock signal; and
a synchronizer control signal generator, responsive to said skew state signal, operating to generate at least one control signal to compensate for said skew between said first clock signal and said second clock signal.
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Accused Products
Abstract
A system and method for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. In a system embodiment, a phase detector is provided for detecting a phase between the first and second clock signals. A skew state detector disposed in communication with the phase detector is operable to generate a skew state signal which tracks a phase relationship between the clock signals. A synchronizer control signal generator responds to the skew state signal by generating at least one control signal to compensate for the skew between the first clock signal and the second clock signal.
32 Citations
20 Claims
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1. A system for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧
- 1, comprising;
a phase detector operable to detect a phase between said first clock signal and said second clock signal;
a skew state detector disposed in communication with said phase detector for generating a skew state signal which tracks a phase relationship between said first clock signal and said second clock signal; and
a synchronizer control signal generator, responsive to said skew state signal, operating to generate at least one control signal to compensate for said skew between said first clock signal and said second clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- 1, comprising;
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9. A method for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧
- 1, comprising;
determining the position of coincident edges of said first clock signal and said second clock signal;
determining if a state transition is necessary based on tracking the position of said coincident edges of said first and second clock signals; and
generating a control signal indicative of said state transition, thereby compensating for said skew between said first clock signal and said second clock signal. - View Dependent Claims (10, 11, 12, 13, 14)
- 1, comprising;
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15. A computer system having an apparatus for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧
- 1, comprising;
means for determining the position of coincident edges of said first clock signal and said second clock signal;
means for determining if a state transition is necessary based on tracking the position of said coincident edges of said first and second clock signals; and
means for generating a control signal indicative of said state transition, thereby compensating for said skew between said first clock signal and said second clock signal. - View Dependent Claims (16, 17, 18, 19, 20)
- 1, comprising;
Specification