Delay locked loop circuitry for clock delay adjustment

• US 20040223571A1
• Filed: 02/14/2003
• Published: 11/11/2004
• Est. Priority Date: 02/06/1997
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kim, Jun, Lee, Thomas H., Stark, Donald C., Johnson, Mark G., Garlepp, Bruno W., Horowitz, Mark A., Lau, Benedict C., Donnelly, Kevin S., Yu, Leung, Chau, Pak Shing, Nguyen, Nhat M., Chan, Yiu-Fai, Tran, Chanh Vi
• Granted Patent: US 7,039,147 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00032 Dc control of switching transistors
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

Claims

1. A method for producing a set of phase vectors, the method comprising the steps of:

producing a set of phase vectors from a set of delay producing elements coupled in series to form a chain, the first delay in the chain receiving a chain-input clock, the chain-input clock coupled to an input clock, wherein any two adjacent phase vectors are separated by an unit delay and all unit delays are equal; and

adjusting the delays between phase vectors such that a selected phase vector is in a predetermined phase relationship with the input clock, wherein the set of phase vectors spans a predetermined degree of phase shift of the input clock.

2. The method of claim 1, wherein the predetermined degree of phase shift of the input clock spanned by the phase vectors is 360 degrees.

3. The method of claim 1, wherein the predetermined degree of phase shift of the input clock spanned by the phase vectors is 180 degrees.

4. The method of claim 1, wherein the predetermined phase relationship between the input clock and the last phase vector is 180 degrees.

5. The method of claim 1, further comprising the step of storing the current adjustment of the delays in the chain, wherein the predetermined phase relationship between the input clock and the selected phase vector and the predetermined degree of phase shift of the input clock are preserved during a period of time when the clock source is not present.

6. The method of claim 1, wherein the step of adjusting the delays between the vectors includes the step of:

detecting the deviation from the predetermined phase relationship between the input clock and the selected phase vector.

7. The method of claim 6, further comprising the step of filtering the detected deviation from the predetermined phase relationship to reduce loop jitter.

8. The method of claim 1, wherein the chain-input clock and the outputs of each delay in the chain are buffered to produce the input clock and the set of phase vectors, respectively.

9. The method of claim 1, wherein a delay element is coupled to the end of the chain so that all phase vectors produced by the chain have the same loading characteristics.

10. The method of claim 1, wherein the chain-input clock is coupled through a buffer to a clock source.

11. The method of claim 10, wherein the buffer is a duty cycle correcting amplifier.

12. A method for generating a predetermined phase relationship between an input clock and an output clock, the method comprising the steps of:

selecting a pair of phase vectors from a set of phase vectors, each vector separated in time from an adjacent vector by an unit delay;

producing the output clock from an interpolator that receives the selected pair of phase vectors;

delaying the output clock from the interpolator by a delay equal to a multiple of the unit delay to produce a feedback clock;

adjusting the selection of a pair of phase vectors received by the interpolator so that the phase of the input clock lies between the selected pair of phase vectors;

detecting the difference in phase between the input clock and the feedback clock;

interpolating between selected pair of vectors so that the feedback clock is in phase with the input clock based on the detected phase difference between the input clock and the feedback clock; and

wherein the output clock from the interpolator has the predetermined phase relationship with the input clock, when the feedback clock is in phase with the input clock, the predetermined phase relationship being a multiple of the unit delay.

13. The method of claim 12, wherein the step of detecting the difference in phase includes the step of filtering the detected phase difference between the input clock and the feedback clock.

14. The method of claim 12, further comprising the step of storing the current selection of phase vectors and the current adjustment of the interpolator, wherein the current selection of phase vectors and the current adjustment of the interpolator are preserved during a period of time when the input clock not is not present or the set of phase vectors is not present.

15. The method of claim 12, wherein the multiple of the unit delay includes zero.

16. The method of claim 12, further comprising the step of delaying the output clock from the interpolator by a delay equal to a multiple of the unit delay to produce the output clock, wherein the output clock has a predetermined phase relationship with the input clock, the predetermined phase relationship being a multiple of the unit delay.

17. The method of claim 16, wherein the output clock may lead or lag the input clock by a multiple of the unit delay.

18. The method of claim 12, wherein the output clock from the interpolator is buffered with a first clock buffer to produce the output clock;

and

wherein the feedback clock is buffered with a second clock buffer to produce the feedback clock, the first and second clock buffers having substantially the same delay and the output clock having a predetermined phase relationship with the input clock, the predetermined phase relationship being a multiple of the unit delay.

19. Circuitry for producing a set of phase vectors, the circuitry comprising:

at least two adjustable delay elements each having a delay adjust signal, the delay elements coupled in series to form a chain for producing a set of phase vectors, wherein at least one phase vector is produced at the output of each delay element and wherein the first delay element in the chain receives a chain-input clock, the chain-input clock coupled to an input clock; and

a delay adjusting circuit receiving the input clock and a selected phase vector, the delay adjusting circuit for adjusting the delays between the phase vectors with the delay adjust signal such that the input clock is in the predetermined phase relationship with the selected phase vector and the set of phase vectors spans a predetermined degree of phase shift of the input clock.

20. The circuitry of claim 19, wherein the predetermined degree of phase shift of the input clock spanned by the phase vectors is 360 degrees.

21. The circuitry of claim 19, wherein the predetermined degree of phase shift of the input clock spanned by the phase vectors is 180 degrees.

22. The circuitry of claim 19, wherein the predetermined phase relationship between the input clock and the last phase vector is 180 degrees.

23. The circuitry of claim 19, further comprising:

a set of buffers each coupled to the output of a delay element in the chain, the set of buffers for producing a set of phase vectors at the output of the set of buffers; and

a clock buffer having an input connected to the chain-input clock, the clock buffer for producing the clock input, wherein the set of buffers and the clock buffer have substantially the same delay.

24. The circuitry of claim 19, wherein a delay element is added to the chain, the delay element receiving the last phase vector in the chain so that all phase vectors produced by the chain have the same loading characteristics.

25. The circuitry of claim 19, wherein the delay adjusting circuit comprises:

a phase detector receiving the input clock and the last phase vector, the phase detector for determining whether the input clock is in a predetermined phase relationship with the last phase vector and for producing a phase detector output signal based on the difference from the predetermined phase relationship between the input clock and last phase vector; and

a control circuit receiving the phase detector output signal and for generating the delay adjust signal based on the phase detector output signal.

26. The circuitry of claim 25, wherein the control circuit includes a digital storage circuit having state information for representing the current delay adjustment of the loop.

27. The circuitry of claim 26, wherein the state information of the digital storage circuit is preserved when the clock source is not present.

28. The circuitry of claim 25, wherein the control circuit comprises:

a counter circuit receiving the phase detector output signal and generating a digital count based on the phase detector output signal; and

a digital to analog converter receiving the digital count and generating the delay adjust signal, wherein the delay adjust signal is an analog signal proportional to the digital count.

29. The circuitry of claim 25, wherein the control circuit comprises:

a filter receiving the phase detector output signal and generating a filtered phase detector output signal for reducing loop jitter;

a counter circuit the counter circuit receiving the filtered phase detector output signal and generating a digital count based on the phase detector output signal; and

a digital to analog converter receiving the digital count and generating the delay adjust signal, wherein the delay adjust signal is an analog signal proportional to the digital count.

30. The circuitry of claim 29, wherein the filter is a digital filter.

31. The circuitry of claim 25, further comprising:

a duty cycle correcting amplifier having an input coupled to a clock source, the duty cycle correcting amplifier generating the chain-input clock; and

a duty cycle correcting circuit receiving the chain-input clock and adjusting the duty cycle correcting amplifier such that the chain-input clock has a duty cycle substantially close to 50%.

32. Circuitry for generating a predetermined phase relationship between a pair of clocks, the circuit comprising:

selection circuitry having as inputs a set of phase vectors and a selection control signal, each vector separated in time from an adjacent vector by an unit delay, the selection circuitry for selecting a pair of phase vectors from the set;

a phase interpolator circuit receiving the selected pair of phase vectors and a phase adjust signal and generating a phase interpolator output clock, the phase interpolator for adjusting the phase of phase interpolator clock, wherein the output clock is coupled to the phase interpolator output clock;

at least one feedback delay element coupled to the phase interpolator output clock to produce a first delayed clock, the feedback delay element delaying the first delayed clock from the phase interpolator output clock by an amount equal to a multiple of the unit delay, wherein a feedback clock is coupled to the first delayed clock; and

a phase adjusting circuit receiving the input clock and the feedback clock, wherein the phase adjusting circuit produces the selection control signal for adjusting the selection of a pair of phase vectors produced by the selection circuitry so that the phase of the input clock lies between the selected pair of phase vectors and wherein the phase adjusting circuit produces the phase adjust signal for adjusting the phase interpolator so that the feedback clock is in phase with the input clock, wherein the output clock has the predetermined phase relationship with the input clock, when the feedback clock is in phase with the input clock, the predetermined phase relationship being a multiple of the unit delay.

33. The circuitry of claim 32, wherein the multiple of the unit delay includes zero.

34. The circuitry of claim 32, further comprising:

at least one output delay element coupled to the phase interpolator output clock to produce the output clock; and

wherein the output delay element delays the output clock delayed by an amount equal to a multiple of the unit delay and wherein the output clock has a predetermined phase relationship with the input clock, the predetermined phase relationship being a multiple of the unit delay.

35. The circuitry of claim 34, wherein the output clock may lead or lag the input clock by a multiple of the unit delay.

36. The circuitry of claim 32, wherein the output clock from the interpolator is buffered with a first clock buffer to produce the output clock and wherein the feedback clock is buffered with a second clock buffer to produce the feedback clock, the first and second clock buffers having substantially the same delay and the output clock having a predetermined phase relationship with the input clock, the predetermined phase relationship being a multiple of the unit delay.

37. The circuitry of claim 32, wherein the phase adjusting circuit comprises:

a phase detector receiving the input clock and the feedback clock, the phase detector for determining whether the feedback clock is in phase with the input clock and for producing a phase detector output based on the difference in phase between the feedback clock and the input clock; and

a control circuit receiving the phase detector output signal, the control circuit producing the selection control signal for,adjusting the selection of a pair of phase vectors generated by the selection circuitry and producing the phase adjust signal for adjusting the phase interpolator.

38. The circuitry of claim 37, wherein the control circuit includes a digital storage circuit having state information for representing the current selection of phase vectors and the adjustment of the phase interpolator.

39. The circuitry of claim 38, wherein the state information of the digital storage circuit is preserved when the input clock not is not present or the set of phase vectors is not present.

40. The circuitry of claim 37, wherein the control circuit includes:

a counter circuit receiving the phase detector output signal and generating a digital count based on the phase detector output signal; and

a digital to analog converter receiving the digital count and generating the phase adjust signal, wherein the phase adjust signal is an analog signal proportional to the digital count.

41. The circuitry of claim 37, wherein the control circuit includes:

a filter receiving the phase detector output signal and generating a filtered phase detector output signal for reducing loop jitter;

a counter circuit receiving the filtered phase detector output signal and generating a digital count based on the phase detector output signal; and

a digital-to-analog converter receiving the digital count and generating the phase adjust signal, wherein the phase adjust signal is an analog signal proportional to the digital count.

42. The circuitry of claim 41, wherein the filter is a digital filter.

43. The circuitry of claim 32, further comprising:

a first duty cycle correcting amplifier receiving the first delayed clock, the first duty cycle correcting amplifier generating the feedback clock;

a second duty cycle correcting amplifier receiving the phase interpolator output clock, the second duty cycle correcting amplifier generating the output clock; and

a duty cycle correcting circuit receiving the feedback clock and adjusting the first and second duty cycle correcting amplifiers such that the feedback clock and output clock have substantially the same duty cycle, wherein the duty cycle is substantially close to 50%.

44. A method for generating a predetermined phase relationship between a pair of clocks, the method comprising the steps of:

operating a first delay locked loop circuitry to generate a set of phase vectors from an input clock, wherein any two adjacent phase vectors are separated by an unit delay and all unit delays are equal and wherein the set of phase vectors spans a predetermined degree of phase shift of the input clock, when the first loop is locked; and

operating a second delay locked loop circuitry to generate the predetermined phase relationship between the pair of clocks, wherein a delayed version of the output clock is in phase to the input clock, when the second loop is locked, the delayed version of the output clock being a multiple of the unit delay between the phase vectors generated from the first loop and the unit delay being derived from the first delayed locked loop.

45. A memory system comprising:

a controller;

a least one memory circuit;

a data bus coupling said controller to said at least one memory circuit;

a data transmitter and data receiver circuit in at least one of said controller and said one memory circuit, at least one of said data transmitter and data receiver being coupled to clock circuitry for producing a set of phase vectors, said clock circuitry including

at least two adjustable delay elements each having a delay adjust signal, the delay elements coupled in series to form a chain for producing a set of phase vectors, wherein at least one phase vector is produced at the output of each delay element and wherein the first delay element in the chain receives a chain-input clock, the chain-input clock coupled to an input clock; and

a delay adjusting circuit receiving the input clock and a selected phase vector, the delay adjusting circuit for adjusting the delays between the phase vectors with the delay adjust signal such that the input clock is in the predetermined phase relationship with the selected phase vector and the set of phase vectors spans a predetermined degree of phase shift of the input clock.