Methods of manufacturing semiconductor devices having a ruthenium layer via atomic layer deposition and associated apparatus and devices

• US 20040224475A1
• Filed: 03/16/2004
• Published: 11/11/2004
• Est. Priority Date: 03/27/2003
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoo, Cha-young, Lee, Jin-il, Lee, Kwang-hee, Lim, Han-jin, Chung, Suk-jin
• Application Number:
  US10/801,208
• Publication Number:
  US 20040224475A1
• Time in Patent Office: Days
• US Class Current: 438/399
• CPC Class Codes: C23C 16/0281 of metallic sub-layers C23C16/029 takes precedence
• CPC Class Codes: C23C 16/18 from metallo-organic compounds
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 28/90 having vertical extensions

Abstract

Methods of fabricating a semiconductor device are provided in which a storage node contact plug is formed on a semiconductor substrate. A ruthenium seed layer is then formed via atomic layer deposition on the storage node contact plug, and a main ruthenium layer is formed on the ruthenium seed layer. The main ruthenium layer and the ruthenium seed layer are patterned to form a lower electrode, and a dielectric layer is formed on the lower electrode. Finally, an upper electrode is formed on the dielectric layer. The upper electrode may be formed by forming a second ruthenium seed layer using atomic layer deposition on the dielectric layer and forming a second main ruthenium layer on the second ruthenium seed layer. The main ruthenium layer and/or the second main ruthenium layer may be formed via chemical vapor deposition.

Claims

1. A method of fabricating an electrode for a microelectronic device, the method comprising:

forming a ruthenium seed layer using atomic layer deposition on a semiconductor substrate;

forming a main ruthenium layer on the ruthenium seed layer; and

patterning the main ruthenium layer and the ruthenium seed layer to form the electrode.

2. The method of claim 1, further comprising:

forming a dielectric layer on the electrode; and

forming an upper electrode on the dielectric layer to provide a capacitor.

3. The method of claim 2, further comprising forming a storage node contact plug on the semiconductor substrate and a storage node that is electrically connected to the storage node contact plug to provide a semiconductor memory device, wherein the ruthenium seed layer is formed on the storage node contact plug.

4. The method of claim 1, wherein forming the ruthenium seed layer using atomic layer deposition comprises:

injecting a ruthenium source into a chamber containing the semiconductor substrate;

then

injecting an O₂-containing gas into the chamber containing the semiconductor substrate; and

then

injecting an H₂-containing gas into the chamber containing the semiconductor substrate.

5. The method of claim 4, further comprising purging the chamber following the injection of the ruthenium source, the injection of the O₂-containing gas, and the injection of the H₂-containing gas.

6. The method of claim 4, wherein the O₂-containing gas comprises an O₂ gas, an O₃ gas, and/or an H₂O gas and the H₂-containing gas comprises an H₂ gas and/or an NH₃ gas.

7. The method of claim 4, wherein at least one of the O₂-containing gas or the H₂-containing gas is supplied in a plasma phase.

8. The method of claim 4, wherein injecting the ruthenium source, injecting the O₂-containing gas, and injecting the H₂-containing gas into the chamber is performed at least twice until the ruthenium seed layer is grown to a desired thickness.

9. The method of claim 1, wherein the ruthenium seed layer is formed to a thickness of about 5 Å

to 50 Å and

wherein the main ruthenium layer is formed to a thickness of 50 Å

to 300 Å

.

10. The method of claim 1, wherein the forming of the main ruthenium layer comprises supplying oxygen at a flow rate of about 1 sccm to 50 sccm and supplying a ruthenium source at a flow rate of about 0.1 ccm to 2 ccm under a pressure of about 0.4 Torr to 0.6 Torr.

11. The method of claim 2, wherein the dielectric layer comprises a tantalum oxide layer.

12. The method of claim 2, wherein the forming of the upper electrode comprises:

forming a second ruthenium seed layer using atomic layer deposition on the dielectric layer; and

forming a second main ruthenium layer on the second ruthenium seed layer.

13. The method of claim 1, wherein the main ruthenium layer is formed using chemical vapor deposition.

14. The method of claim 1, wherein the ruthenium seed layer has an oxygen concentration of less than 5%.

15. A method of forming a ruthenium layer in a semiconductor device, the method comprising:

using atomic layer deposition to form a ruthenium seed layer on a semiconductor substrate;

using a gas containing hydrogen to remove impurities from the ruthenium seed layer; and

forming a main ruthenium layer on the ruthenium seed layer.

16. The method of claim 15, wherein the ruthenium seed layer is formed on a non-planar surface.

17. The method of claim 16, wherein the non-planar surface includes a recess having a height that is greater than a width of the recess.

18. The method of claim 16, wherein the non-planar surface includes a recess having substantially vertical sidewalls.

19. The method of claim 16, wherein the ruthenium seed layer has a substantially uniform thickness.

20. The method of claim 15, wherein using atomic layer deposition to form a ruthenium seed layer on a semiconductor substrate comprises:

introducing a ruthenium source into a chamber containing the semiconductor substrate;

purging the chamber; and

then

introducing an oxygen-containing gas into the chamber; and

purging the chamber.

21. The method of claim 20, wherein the oxygen-containing gas and the gas containing hydrogen are supplied in a plasma phase.

22. The method of claim 15, wherein the ruthenium seed layer is formed on a contact layer.

23. The method of claim 15, wherein the main ruthenium layer is deposited using chemical vapor deposition techniques and wherein the ruthenium seed layer is a non-planar layer having a substantially uniform thickness.

24. The method of claim 15, wherein the ruthenium seed layer is formed to a thickness of about 5 Å

to 50 Å and

wherein the main ruthenium layer is formed to a thickness of 50 Å

to 300 Å

.

25. A method of manufacturing a semiconductor memory device, the method comprising:

forming an interlayer dielectric and a storage node contact plug on a semiconductor substrate;

forming a first ruthenium seed layer using atomic layer deposition on the storage node contact plug;

forming a first main ruthenium layer using chemical vapor deposition on the first ruthenium seed layer;

forming a lower electrode by polishing the first main ruthenium layer and the first ruthenium seed layer using chemical mechanical polishing;

forming a dielectric layer on the lower electrode;

forming a second ruthenium seed layer using atomic layer deposition on the dielectric layer; and

completing an upper electrode by forming a second main ruthenium layer using chemical vapor deposition on the second ruthenium seed layer.

26. The method of claim 25, further comprising:

forming a sacrificial oxide layer on the interlayer dielectric and the storage node contact plug;

forming a lower electrode region by etching the sacrificial oxide layer until the storage node contact plug is exposed; and

wherein the first ruthenium seed layer is formed on the lower electrode region and the sacrificial oxide layer.

27. A semiconductor device having a capacitor, comprising:

a lower electrode on a semiconductor substrate, the lower electrode comprising a first ruthenium seed layer having an oxygen content of less than 5% and a first main ruthenium layer on the first ruthenium seed layer;

a dielectric layer on the lower electrode; and

an upper electrode comprising a second ruthenium seed layer having an oxygen content of less than 5% and a second main ruthenium layer on the ruthenium seed layer.

28. The semiconductor device of claim 27, wherein the first ruthenium seed layer has a thickness of about 5 Å

to 50 Å and

the first main ruthenium layer has a thickness of at least 50 Å

.

29. The semiconductor device of claim 28, wherein the dielectric layer comprises a tantalum oxide layer.

30. The semiconductor device of claim 27, wherein the first ruthenium seed layer has a substantially uniform thickness and an upper surface of the first ruthenium seed layer is non-planar.

31. The semiconductor device of claim 27, wherein the first ruthenium seed layer is formed in a recess that has substantially vertical sidewalls.

32. An apparatus for manufacturing a ruthenium layer on a semiconductor substrate, the apparatus comprising:

an atomic layer deposition chamber that is configured to deposit a ruthenium seed layer on the semiconductor substrate via atomic level deposition;

a chemical vapor deposition chamber that is configured to deposit a main ruthenium layer on the ruthenium seed layer via chemical vapor deposition; and

a transfer module operatively connected to the atomic layer deposition chamber and the chemical vapor deposition chamber that is configured to transfer the semiconductor substrate between the atomic level deposition chamber and the chemical vapor deposition chamber.

33. The apparatus of claim 32, wherein the transfer module is configured to transfer the semiconductor substrate between the atomic level deposition chamber and the chemical vapor deposition chamber without breaking vacuum.