Adaptive diversity receiver architecture

• US 20040224655A1
• Filed: 05/06/2003
• Published: 11/11/2004
• Est. Priority Date: 05/06/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: AMI Semiconductor Inc (ON Semiconductor Corporation)
• Inventors: Christensen, Craig L., Petrov, Andrei R.
• Granted Patent: US 7,006,809 B2
• Time in Patent Office: Days
• US Class Current: 455/226.1
• CPC Class Codes: H04B 7/0817 with multiple receivers and antenna path selection
• CPC Class Codes: H04B 7/084 Equal gain combining, only phase adjustments antenna beam scanning or forming by phase or amplitude control H01Q3/26, e.g. phased arrays
• CPC Class Codes: H04B 7/0871 using different reception schemes, at least one of them being a diversity reception scheme
• CPC Class Codes: H04B 7/0874 using subgroups of receive antennas

Abstract

A diversity receiver circuit that adaptively selects a variable number of one or more antennas for use in improving signal quality. Each antenna is provided its own receiver that each generates a representation of a received signal. This adaptive selection offers high dynamic adaptability in using the appropriate antennas and receivers at the appropriate time to thereby improving signal-to-noise ratio. The receivers may be direct conversion receivers that implement up-conversion of the baseband signal to reduce DC offset and 1/f noise characteristic of direct conversion architectures.

Claims

1. A diversity receiver circuit comprising the following:

a first receiver configured to receive a first representation of a signal on a first antenna and process the first representation of the signal;

a second receiver configured to receive a second representation of the signal on a second antenna and process the second represent of the signal; and

means for adaptively phase shift summing the processed first and second representations of the signal only if the processed first and second representations have sufficient strength, and otherwise selecting only one of the processed first and second representations of the signal for further processing.

2. A diversity receiver circuit in accordance with claim 1, wherein each element of the diversity receiver circuit is fabricated on a single integrated die.

3. A diversity receiver circuit in accordance with claim 1, wherein the means for adaptively phase shift summing the processed first and second representations of the signal only if the processed first and second representations have sufficient strength, and otherwise selecting only one of the processed first and second representations of the signal for further processing comprise the following:

a phase shifter configured to receive the processed first representation of the signal at least when the processed first representation of the signal exceeds a first threshold value, the phase shifter further configured to generate a phase shifted version of the processed first representation of the signal at least when the processed first representation of the signal exceeds the first threshold value; and

a summer configured to sum the phase shifted version of the processed first representation of the signal with the processed second representation of the signal at least when both of the following conditions are true;

the processed first representation of the signal exceeds the first threshold value, and

the processed second representation of the signal exceeds a second threshold value.

4. A diversity receiver circuit in accordance with claim 3, wherein the first and second threshold values are the same threshold value.

5. A diversity receiver circuit in accordance with claim 3, wherein the first and second threshold values are different threshold values.

6. A diversity receiver circuit in accordance with claim 3, further comprising the following:

a first comparator configured to receive and compare the processed first representation of the signal and the first threshold value, the first comparator configured to couple the processed first representation of the signal with the phase shifter if the processed first representation of the signal exceeds the first threshold value.

7. A diversity receiver circuit in accordance with claim 6, further comprising the following:

a second comparator configured to receive and compare the processed second representation of the signal and the second threshold value, the second comparator configured to couple the processed second representation of the signal with the summer when the processed second representation of the signal exceeds the second threshold value.

8. A diversity receiver circuit in accordance with claim 7, wherein the phase shifter is a first phase shifter, the diversity receiver circuit further comprising the following:

a second phase shifter configured to receive the processed second representation of the signal at least when the processed second representation of the signal exceeds the second threshold value, the second phase shifter further configured to generate a phase shifted version of the processed second representation of the signal at least when the processed second representation of the signal exceeds the second threshold value.

9. A diversity receiver circuit in accordance with claim 8, wherein the summer is configured to sum the phase shifted version of the processed first representation of the signal and the phase shifted version of the processed second representation of the signal at least when both of the following conditions are true:

the processed first representation of the signal exceeds the first threshold value, and

the processed second representation of the signal exceeds a second threshold value.

10. A diversity receiver circuit in accordance with claim 8, further comprising the following:

a phase detector configured to detect when the phase shifted version of the processed first representation of the signal is out of phase with the phase shifted version of the processed second representation of the signal, and is configured to control either or both of the first phase shifter and the second phase shifter so that the processed first and second representations of the signal received by the summer tend to be towards a relatively fixed phase shift with each other.

11. A diversity receiver circuit in accordance with claim 8, wherein the relatively fixed phase shift is approximately ninety degrees.

12. A diversity receiver circuit in accordance with claim 1, further comprising the following:

a third receiver configured to receive a third representation of a signal on a third antenna and process the third representation of the signal,

wherein the means for phase shift summing comprises a mean for phase shift summing the processed first, second, and third representations of the signal only if the processed first, second, and third representations have sufficient strength, and otherwise selecting less than all of the processed first, second and third representations of the signal for further processing.

13. A diversity receiver circuit in accordance with claim 1, wherein the first receiver is a direct conversion receiver having an in-phase branch and a quadrature-phase branch.

14. A diversity receiver circuit in accordance with claim 13, wherein the direct conversion receiver comprises the following:

an in-phase amplifier configured to receive and amplify an in-phase differential signal that represents an in-phase portion of the processed first representation of the signal;

an in-phase summer configured to receive and sum the amplified in-phase differential signal;

a quadrature-phase amplifier configured to receive and amplify the quadrature-phase differential signal that represents a quadrature-phase portion of the processed first representation of the signal;

a quadrature-phase summer configured to receive and sum the amplified quadrature-phase differential signal, and

a limiting amplifier configured to receive and amplify in a limited fashion the difference between the summed in-phase signal and the summed quadrature-phase signal.

15. A diversity receiver circuit in accordance with claim 14, wherein the direct conversion receiver further comprising the following:

a band pass filter configured to receive and filter the limit amplified signal.

16. A diversity receiver circuit in accordance with claim 15, wherein the direct conversion receiver further comprises the following:

an in-phase down-converting mixer that is configured to down-convert a received modulated signal to thereby generate an in-phase portion of a baseband signal;

an in-phase low pass filter that is coupled to the in-phase down-converting mixer so as to filter high frequency components of the in-phase down-converted signal to thereby generate an in-phase filtered down-converted signal;

an in-phase up-converting mixer that is coupled to the in-phase low pass filter so as to receive and up-convert the in-phase filtered down-converted signal to generate the in-phase differential signal, wherein there are no active components that operate on the in-phase down-converted signal prior to being up-converted;

a quadrature-phase down-converting mixer that is configured to down-convert the received modulated signal to thereby generate a quadrature-phase portion of the baseband signal;

a quadrature-phase low pass filter that is coupled to the quadrature-phase down-converting mixer so as to filter high frequency components of the quadrature-phase down-converted signal to thereby generate a quadrature-phase down-converted signal; and

a quadrature-phase up-converting mixer that is coupled to the quadrature-phase low pass filter so as to receive and up-convert the quadrature-phase filtered down-converted signal to generate the quadrature-phase differential signal, wherein there are no active components that operate on the quadrature-phase down-converted signal prior to being up-converted.

17. A diversity receiver circuit comprising the following:

a first receiver configured to receive a first representation of a signal on a first antenna and process the first representation of the signal;

a second receiver configured to receive a second representation of the signal on a second antenna and process the second represent of the signal;

a phase shifter configured to receive the processed first representation of the signal at least when the processed first representation of the signal exceeds a first threshold value, the phase shifter further configured to generate a phase shifted version of the processed first representation of the signal at least when the processed first representation of the signal exceeds the first threshold value; and

a summer configured to sum the phase shifted version of the processed first representation of the signal with the processed second representation of the signal at least when both of the following conditions are true;

the processed first representation of the signal exceeds the first threshold value, and

the processed second representation of the signal exceeds a second threshold value.

18. A diversity receiver circuit in accordance with claim 17, wherein each element of the diversity receiver circuit is fabricated on a single integrated die.

19. A diversity receiver circuit in accordance with claim 17, further comprising the following:

a first comparator configured to receive and compare the processed first representation of the signal and the first threshold value, the first comparator configured to couple the processed first representation of the signal with the phase shifter if the processed first representation of the signal exceeds the first threshold value.

20. A diversity receiver circuit in accordance with claim 19, further comprising the following:

a second comparator configured to receive and compare the processed second representation of the signal and the second threshold value, the second comparator configured to couple the processed second representation of the signal with the summer when the processed second representation of the signal exceeds the second threshold value.

21. A diversity receiver circuit in accordance with claim 20, wherein the phase shifter is a first phase shifter, the diversity receiver circuit further comprising the following:

a second phase shifter configured to receive the processed second representation of the signal at least when the processed second representation of the signal exceeds the second threshold value, the second phase shifter further configured to generate a phase shifted version of the processed second representation of the signal at least when the processed second representation of the signal exceeds the second threshold value.

22. A diversity receiver circuit in accordance with claim 21, wherein the summer is configured to sum the phase shifted version of the processed first representation of the signal and the phase shifted version of the processed second representation of the signal at least when both of the following conditions are true:

the processed first representation of the signal exceeds the first threshold value, and

the processed second representation of the signal exceeds a second threshold value.

23. A diversity receiver circuit in accordance with claim 21, further comprising the following:

a phase detector configured to detect when the phase shifted version of the processed first representation of the signal is out of phase with the phase shifted version of the processed second representation of the signal, and is configured to control either or both of the first phase shifter and the second phase shifter so that the processed first and second representations of the signal received by the summer tend to be towards a relatively fixed phase shift with each other.

24. A diversity receiver circuit in accordance with claim 21, wherein the relatively fixed phase shift is approximately ninety degrees.

25. A diversity receiver circuit in accordance with claim 17, further comprising the following:

a third receiver configured to receive a third representation of a signal on a third antenna and process the third representation of the signal,

wherein the means for phase shift summing comprises a mean for phase shift summing the processed first, second, and third representations of the signal only if the processed first, second, and third representations have sufficient strength, and otherwise selecting less than all of the processed first, second and third representations of the signal for further processing.

26. A diversity receiver circuit in accordance with claim 17, wherein the first receiver is a direct conversion receiver having an in-phase branch and a quadrature-phase branch.

27. A diversity receiver circuit in accordance with claim 26, wherein the direct conversion receiver comprises the following:

an in-phase amplifier configured to receive and amplify an in-phase differential signal that represents an in-phase portion of the processed first representation of the signal;

an in-phase summer configured to receive and sum the amplified in-phase differential signal;

a quadrature-phase amplifier configured to receive and amplify the quadrature-phase differential signal that represents a quadrature-phase portion of the processed first representation of the signal;

a quadrature-phase summer configured to receive and sum the amplified quadrature-phase differential signal, and

a limiting amplifier configured to receive and amplify in a limited fashion the difference between the summed in-phase signal and the summed quadrature-phase signal.

28. A diversity receiver circuit in accordance with claim 27, wherein the direct conversion receiver further comprising the following:

a band pass filter configured to receive and filter the limit amplified signal.

29. A diversity receiver circuit in accordance with claim 28, wherein the direct conversion receiver further comprises the following:

an in-phase down-converting mixer that is configured to down-convert a received modulated signal to thereby generate an in-phase portion of a baseband signal;

an in-phase low pass filter that is coupled to the in-phase down-converting mixer so as to filter high frequency components of the in-phase down-converted signal to thereby generate an in-phase filtered down-converted signal;

an in-phase up-converting mixer that is coupled to the in-phase low pass filter so as to receive and up-convert the in-phase filtered down-converted signal to generate the in-phase differential signal, wherein there are no active components that operate on the in-phase down-converted signal prior to being up-converted;

a quadrature-phase down-converting mixer that is configured to down-convert the received modulated signal to thereby generate a quadrature-phase portion of the baseband signal;

a quadrature-phase low pass filter that is coupled to the quadrature-phase down-converting mixer so as to filter high frequency components of the quadrature-phase down-converted signal to thereby generate a quadrature-phase down-converted signal; and

a quadrature-phase up-converting mixer that is coupled to the quadrature-phase low pass filter so as to receive and up-convert the quadrature-phase filtered down-converted signal to generate the quadrature-phase differential signal, wherein there are no active components that operate on the quadrature-phase down-converted signal prior to being up-converted.