Method and structure to develop a test program for semiconductor integrated circuits

• US 20040225459A1
• Filed: 02/06/2004
• Published: 11/11/2004
• Est. Priority Date: 02/14/2003
• Status: Abandoned Application

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Adachi, Toshiaki, Singh, Harsanjeet, Tahara, Yoshihumi, Krishnaswamy, Ramachandran, Chen, Leon, Pramanick, Ankan, Elston, Mark
• Application Number:
  US10/772,434
• Publication Number:
  US 20040225459A1
• Time in Patent Office: Days
• US Class Current: 702/57
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture

Abstract

Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.

Claims

1. A method for developing a test program in general purpose C/C++ constructs, the test program for testing a semiconductor integrated circuit (IC) in a semiconductor test system, the method comprising:

describing test system resources, test system configuration, and module configuration in general-purpose C/C++ constructs for the development of a test program to test the IC on the semiconductor test system;

describing a test sequence in general-purpose C/C++ constructs for the development of the test program to test the IC on the semiconductor test system;

describing a test plan in general-purpose C/C++ constructs for the development of the test program to test the IC on the semiconductor test system;

describing test conditions in general-purpose C/C++ constructs for the development of the test program to test the IC on the semiconductor test system;

describing test patterns in general-purpose C/C++ constructs for the development of the test program to test the IC on the semiconductor test system; and

describing timing of the test patterns in general-purpose C/C++ constructs for the development of the test program to test the IC on the semiconductor test system.

2. The method of claim 1, wherein describing test system resources comprises:

specifying a resource type, wherein the resource type is associated with at least one test module for applying a test to the IC;

specifying a parameter type associated with the resource type, and

specifying a parameter of the parameter type.

3. The method of claim 1, wherein describing test system configuration comprises:

specifying a site controller for controlling at least one test module, each test module for applying a test to the IC; and

specifying an input port of a module connection enabler,

wherein the test system couples the site controller to the module connection enabler at the input port, and the module connection enabler couples the site controller to the at least one test module.

4. The method of claim 3, wherein the module connection enabler is a switch matrix.

5. The method of claim 1, wherein describing module configuration comprises:

specifying a module identifier for specifying a module type;

specifying executable code for controlling a test module of the module type specified by the module identifer, the test module for applying a test to the IC; and

specifying a resource type associated with the test module.

6. The method of claim 5, the method further comprising specifying a slot identifier for specifying an output port of a module connection enabler, wherein the test system couples the test module to the module connection enabler at the output port, and the module connection enabler couples the test module to a corresponding site controller.

7. The method of claim 6, wherein the module connection enabler is a switch matrix.

8. The method of claim 5, wherein the executable code is a dynamic link library.

9. The method of claim 5, further comprising specifying a vendor identifier for identifying the provider of the test module.

10. The method of claim 5, further comprising specifying an identifier of the maximum number of resource units available in connection with the resource type.

11. The method of claim 5, wherein the resource type is digital tester pins and the resource units are tester channels.

12. The method of claim 5, wherein the resource type is analog tester pins and the resource units are tester channels.

13. The method of claim 5, wherein the resource type is RF tester pins and the resource units are tester channels.

14. The method of claim 5, wherein the resource type is power supply pins and the resource units are tester channels.

15. The method of claim 5, wherein the resource type is digitizer pins and the resource units are tester channels.

16. The method of claim 5, wherein the resource type is arbitrary waveform generation pins and the resource units are tester channels.

17. The method of claim 5, wherein the resource type is associated with resource units, the method further comprising specifying an indicator relating to which resource units are disabled.

19. The method of claim 1, wherein describing test conditions comprises:

specifying at least one test condition group.

20. The method of claim 19, wherein describing test conditions further comprises:

specifying at least one specification set including at least one variable; and

specifying a selector for selecting an expression to be bound to a variable.

21. The method of claim 20, wherein association of the test condition group with a selector for the at least one specification set defines a test condition.

22. The method of claim 21, wherein the test condition is an object.

23. The method of claim 1, wherein describing a test sequence comprises specifying:

a result of executing a flow or test;

an action based upon the result; and

a transition to another flow or test based upon the result.

18. The method of claim 18, wherein resource units indicated as disabled represent defective resource units of the test module.