BUS TO MULTIPLE JTAG BUS BRIDGE

• US 20040225783A1
• Filed: 07/30/2001
• Published: 11/11/2004
• Est. Priority Date: 07/30/2001
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: MacIorowski, David R., Mantey, Paul John, Erickson, Michael John
• Application Number:
  US09/918,024
• Publication Number:
  US 20040225783A1
• Time in Patent Office: Days
• US Class Current: 710/200
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

A bus bridge is capable of transferring information between a first serial bus and a target serial bus. The bridge is capable of operating as a bus slave on the first serial bus, and as a bus master on the target serial bus. The first serial bus in a particular embodiment is an IIC serial bus, while the target serial bus is a JTAG bus. There may be additional target serial busses, and there is a selection apparatus whereby commands may be directed to a particular target serial bus.

Claims

1-5. -5. (Cancelled)

7-8. -8. (cancelled)

9. A bus bridge comprising:

a first serial bus interface, the first serial bus interface operable as a bus slave;

apparatus for selecting a particular target serial bus port of a plurality of target serial bus ports, the apparatus for selecting a particular target bus port addressable through the first bus interface, wherein the plurality of target ports comprises at least two JTAG bus ports;

apparatus for transferring information between the first serial bus interface and the particular target serial bus port, the apparatus for transferring information operable as a bus master on the particular bus port.

11. The bus bridge of claim 9, wherein the first serial bus interface is an IIC bus interface.

12. The bus bridge of claim 11, wherein the apparatus for transferring information between the first bus interface and the particular target serial bus port bus ports comprises at least one FIFO.

13. The bus bridge of claim 12, further comprising a bypass mechanism whereby data may be communicated between the first serial bus interface and the particular target serial bus without using the at least one FIFO.

14. The bus bridge of claim 13, implemented in an Field Programmable Gate Array (FPGA) having an associated EEPROM for storing configuration code.

15. The bus bridge of claim 14, wherein a serial bus port of the target serial bus ports is coupled to the EEPROM, and wherein the EEPROM may be erased and written through the serial bus.

16. The bus bridge of claim 15, wherein the serial bus port of the target serial busses that is coupled to the EEPROM is also coupled to a configuration header.

17. The bus bridge of claim 11, implemented in a bus bridge FPGA having an EEPROM associated therewith for storing configuration code, wherein a selected serial bus port of the target serial bus ports is coupled to the EEPROM associated with the bus bridge FPGA, and wherein the EEPROM associated with the bus bridge FPGA may be erased and written through the selected target serial bus port, thereby permitting modification of the bus bridge.

21. The bus bridge of claim 17, wherein the apparatus for transferring information has a bypass mode such that the EEPROM associated with the bus bridge FPGA can be erased and written without using the at least one FIFO buffer

10. (Cancelled)

18. A bus bridge comprising:

a first serial bus interface, the first serial bus interface operable as a bus slave;

a target serial bus interface comprising a plurality of target serial bus ports;

selection logic coupled such that the first serial bus interface can designate a selected target serial bus port of the plurality of target serial bus ports, and wherein the target serial bus interface is operable as a bus master on the selected target serial bus port; and

apparatus coupling the first serial bus interface to the target serial bus interface, such that commands received by the first bus interface are capable of causing execution of commands by the target serial bus interface on the selected target serial bus port, the apparatus coupling the first serial bus interface to the target serial bus interface further comprising at least one First-In-First-Out (FIFO) buffer and a status register having flags for detecting data in the at least one FIFO buffer;

wherein the target serial bus interface is a Joint Test Action Group (JTAG) bus interface.

6. The bus bridge of claim 18, wherein the first serial bus interface is an Inter-Integrated Circuit (IIC) bus interface.

19. The bus bridge of claim 18, implemented in a bus bridge FPGA having an EEPROM associated therewith for storing configuration code, wherein a selected serial bus port of the target serial bus ports is coupled to the EEPROM associated with the bus bridge FPGA, and wherein the EEPROM associated with the bus bridge FPGA may be erased and written through the selected target serial bus port, thereby permitting modification of the bus bridge.

20. The bus bridge of claim 19, wherein the apparatus coupling the first serial bus interface to the target serial bus interface has a bypass mode such that the EEPROM associated with the bus bridge FPGA can be erased and written without using the at least one FIFO buffer.