Self-optimizing crossbar switch

• US 20040225787A1
• Filed: 05/31/2001
• Published: 11/11/2004
• Est. Priority Date: 05/31/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Grenier, Lisa C., Ma, James H.
• Granted Patent: US 6,925,520 B2
• Time in Patent Office: Days
• US Class Current: 710/260
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: H04L 49/101 using crossbar or matrix

Abstract

A crossbar switch is disclosed. The crossbar switch comprises a plurality of input sorting units and a plurality of merge and interleave units. Each input sorting unit is capable of receiving from a respective device an access request to any one of a plurality of physical memory devices. Each merge and interleave unit is capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device. Also disclosed is method implemented by the crossbar switch.

Claims

1. A crossbar switch, comprising:

a plurality of input sorting units, each input sorting unit capable of receiving from a respective device an access request to any one of a plurality of physical memory devices;

a plurality of merge and interleave units, each merge and interleave unit capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device.

2. The crossbar switch of claim 1, further comprising a plurality of translation circuits and wherein each of the input sorting units receives the access requests through a respective one of the translation circuits.

3. The crossbar switch of claim 2, wherein each of the translation circuits is capable of receiving an opcode and a virtual address from their respective device, translating the opcode to determine whether the access request is a read or a write, and mapping the virtual address into a physical address, and forwarding the translated opcode and mapped physical address to its respective input sorting unit.

4. The crossbar switch of claim 1, wherein each of the input sorting units includes a buffer and is capable of buffering the access requests from its respective physical memory device.

5. The crossbar switch of claim 4, wherein the buffer is a first-in, first-out queue.

6. The crossbar switch of claim 4, wherein each of the input sorting units is capable of stalling its respective device when its buffer is full.

7. The crossbar switch of claim 1, wherein each merge and interleave unit includes:

a priority generator for each input sorting unit capable of;

receiving a plurality of characteristics for the access request received by the input sorting unit;

receiving a plurality of operational characteristics; and

generating a composite request priority from the characteristics of the access

requests and the operational characteristics;

a priority compare circuit capable of;

comparing the composite request priorities generated by the priority generators; and

selecting one access request predicated on the comparison of the composite request priorities; and

a request multiplexer controlled by the priority compare circuit to output the selected access request.

8. The crossbar switch of claim 7, wherein the merge and interleave unit further includes:

a plurality of programmable registers;

a decode unit receiving the selected request from the request multiplexer to determine whether the selected request is a register operation and, if so, to send a plurality of control and data signals to the registers; and

an output multiplexer for combining register read data with request data for output.

9. The crossbar switch of claim 1, further comprising:

a plurality of read buffers capable of receiving and buffering read data from a respective one of the physical memory devices; and

a plurality of output management units capable of receiving read data from the read buffers and forwarding the received read data to a respective one of the devices that generated the access request associated with the read data.

10. The crossbar switch of claim 1, further comprising a plurality of memory interfaces capable of receiving the selected access request from a respective one of the plurality of merge and interleave units and forwarding the selected access request to a respective one of the physical memory devices.

11. A crossbar switch, comprising a plurality of arbitration and select units, each arbitration and select unit including:

a plurality of front ends, each front end comprising;

a translation circuit capable of processing an access request received from a respective device;

an input sorting unit capable of buffering and forwarding the processed access request;

an output management unit capable of receiving read data generated by the access request and forwarding the received read data to the respective device; and

a plurality of back ends, each back end comprising;

a merge and interleave unit capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests, and forwarding the selected request for implementation on a respective memory device; and

a read buffer capable of receiving, buffering, and forwarding read data received from the respective memory device to the output management unit of the front end that issued a previously selected access request that generated the read data.

12. The crossbar switch of claim 11, wherein each back end further comprises a memory interface through which the merge and interleave unit forwards the selected request.

13. The crossbar switch of claim 11, wherein each of the translation circuits is capable of receiving an opcode and a virtual address from their respective device, translating the opcode to determine whether the access request is a read or a write, and mapping the virtual address into a physical address, and forwarding the translated opcode and mapped physical address to its respective input sorting unit.

14. The crossbar switch of claim 11, wherein each of the input sorting units includes a request buffer and is capable of buffering the access requests from its respective physical memory device.

15. The crossbar switch of claim 14, wherein the request buffer is a first-in, first-out queue.

16. The crossbar switch of claim 14, wherein each of the input sorting units is capable of stalling its respective device when its request buffer is full.

17. The crossbar switch of claim 11, wherein each merge and interleave unit includes:

a priority generator for each input sorting unit capable of;

receiving a plurality of characteristics for the access request received by the input sorting unit;

receiving a plurality of operational characteristics; and

generating a composite request priority from the characteristics of the access requests and the operational characteristics;

a priority compare circuit capable of;

comparing the composite request priorities generated by the priority generators; and

selecting one access request predicated on the comparison of the composite request priorities; and

a request multiplexer controlled by the priority compare circuit to output the selected access request.

18. The crossbar switch of claim 17, wherein each merge and interleave unit further includes:

a plurality of programmable registers;

a decode unit receiving the selected request from the request multiplexer to determine whether the selected request is a register operation and, if so, to send a plurality of control and data signals to the registers; and

an output multiplexer for combining register read data with request data for output.

19-54. -54. Cancelled.

55. A crossbar switch, comprising a plurality of arbitration and select units, each arbitration and select unit including:

a plurality of front ends, each front end further including an input sorting unit capable of receiving from a respective device an access request to any one of a plurality of physical memory devices;

a plurality of back ends, each back end further including merge and interleave unit capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device.

56. The crossbar switch of claim 55, wherein each front end further comprises a Glue logic unit and wherein each of the input sorting units receives the access requests through a respective one of the Glue logic units.

57. The crossbar switch of claim 56, wherein each of the translation circuits is capable of receiving an opcode and a virtual address from their respective device, translating the opcode to determine whether the access request is a read or a write, and mapping the virtual address into a physical address, and forwarding the translated opcode and mapped physical address to its respective input sorting unit.

58. The crossbar switch of claim 55, wherein each of the input sorting units includes a buffer and is capable of buffering the access requests from its respective physical memory device.

59. The crossbar switch of claim 58, wherein the buffer is a first-in, first-out queue.

60. The crossbar switch of claim 58, wherein each of the input sorting units is capable of stalling its respective device when its buffer is full.

61. (Previously presented) The crossbar switch of claim 55, wherein each merge and interleave unit includes:

a priority generator for each input sorting unit capable of;

receiving a plurality of characteristics for the access request received by the input sorting unit;

receiving a plurality of operational characteristics; and

generating a composite request priority from the characteristics of the access requests and the operational characteristics;

a priority compare circuit capable of;

comparing the composite request priorities generated by the priority generators; and

selecting one access request predicated on the comparison of the composite request priorities; and

a request multiplexer controlled by the priority compare circuit to output the selected access request.

62. The crossbar switch of claim 61, wherein each merge and interleave unit further includes:

a plurality of programmable registers;

a decode unit receiving the selected request from the request multiplexer to determine

whether the selected request is a register operation and, if so, to send a plurality of control and data signals to the registers; and

an output multiplexer for combining register read data with request data for output.

63. The crossbar switch of claim 55, wherein:

each back end further includes a read buffer capable of receiving and buffering read data from a respective one of the physical memory devices; and

each front end further includes an output management unit capable of receiving read data from the read buffers and forwarding the received read data to a respective one of the devices that generated the access request associated with the read data.

64. The crossbar switch of claim 55, wherein each back end further comprises a memory interface capable of receiving the selected access request from the merge and interleave unit and forwarding the selected access request to a respective one of the physical memory devices.

65. A crossbar switch, comprising a plurality of arbitration and select units, each arbitration and select unit including:

a plurality of front ends, each front end comprising;

means for processing an access request received from a respective device;

means for buffering and forwarding the processed access request;

means for receiving read data generated by the access request and forwarding

the received read data to the respective device; and

a plurality of back ends, each back end comprising;

means for arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests, and forwarding the selected request for implementation on a respective memory device; and

means for receiving, buffering, and forwarding read data received from the respective memory device to the output management unit of the front end that issued a previously selected access request that generated the read data.

66. The crossbar switch of claim 65, wherein each back end further comprises a memory interface through which the merge and interleave unit forwards the selected request.

67. The crossbar switch of claim 65, wherein each processing means is further capable of receiving an opcode and a virtual address from their respective device, translating the opcode to determine whether the access request is a read or a write, and mapping the virtual address into a physical address, and forwarding the translated opcode and mapped physical address to its respective input sorting unit.

68. The crossbar switch of claim 65, wherein each of the processed access request buffering means includes a buffer and is capable of buffering the access requests from its respective physical memory device.

69. The crossbar switch of claim 68, wherein the buffer is a first-in, first-out queue.

70. The crossbar switch of claim 68, wherein each of the processed access request buffering means is capable of stalling its respective device when its buffer is full.

71. The crossbar switch of claim 65, wherein each arbitration and selection means includes:

means for receiving a plurality of characteristics for the access request received by the input sorting unit, receiving a plurality of operational characteristics, and generating a composite request priority from the characteristics of the access requests and the operational characteristics;

means for comparing the composite request priorities generated by the priority generators, and selecting one access request predicated on the comparison of the composite request priorities; and

means for multiplexing signals, the multiplexing means being controlled by the comparing means to output the selected access request.

72. The crossbar switch of claim 71, wherein each arbitration and selection means further includes:

means for storing programmable weights;

a decode unit receiving the selected request from the multiplexing means to determine whether the selected request is a register operation and, if so, to send a plurality of control and data signals to the storage means;

and means for combining register read data with request data for output.

73. The crossbar switch of claim 65, wherein:

each back end further includes means for receiving and buffering read data from a respective one of the physical memory devices; and

each front end further includes means for receiving read data from the read buffers and forwarding the received read data to a respective one of the devices that generated the access request associated with the read data.

74-89. -89. Cancelled.

90. A crossbar switch, comprising:

means for receiving a plurality of access requests from a plurality of devices, each access request being received by a respective input sorting unit associated with the respective one of the devices issuing the respective access request;

means for forwarding a plurality of received access requests to a plurality of merge and interleave units, each merge and interleave unit being associated with a respective one of a plurality of memory devices;

means for receiving at one of the merge and interleave units a plurality of forwarded access requests;

means for dynamically selecting a respective one from among forwarded access requests; and

means for forwarding the selected access request to a respective one among a plurality of memory devices associated with the merge and interleave unit.

91. The crossbar switch of claim 90, further comprising at least one of:

means for issuing the plurality of access requests;

means for implementing the selected access request on the respective memory device; and

means for returning read data from the respective memory device responsive to the selected access request.

92. The crossbar switch of claim 91, wherein the means for returning the read data includes:

means for buffering the read data in a read buffer associated with the respective memory device;

means for forwarding the read data to an output management unit associated with a respective one of the devices that issued a previously selected access request resulting in the return of the read data.

93. The crossbar switch of claim 90, further comprising, for each access request:

means for processing the access request; and

means for forwarding the processed access request to the respective input sorting unit.

94. The crossbar switch of claim 93, wherein the means for processing the access request includes:

means for receiving an opcode and a virtual address from the respective device;

means for translating the opcode to determine whether the access request is a read or a write;

means for mapping the virtual address into a physical address; and

means for forwarding the translated opcode and mapped physical address to the respective input sorting unit.

95. The crossbar switch of claim 90, wherein the means for receiving the access requests includes means for receiving a plurality of characteristics for the access requests.

96. The crossbar switch of claim 95, wherein the means for dynamically selecting the particular access request includes:

means for ascertaining a plurality of operational characteristics;

means for assigning a weight factor to each characteristic of the access requests;

means for assigning a weight factor to each operational characteristic;

means for obtaining a composite request priority for each access request from the access request'"'"'s respective assigned weight factors;

means for comparing the composite request priorities of the access requests; and

means for selecting the particular access requests predicated on the comparison.

97. The crossbar switch of claim 96, wherein the means for obtaining the composite request priority for each access request includes means for summing the assigned weight factors.

98. The crossbar switch of claim 96, wherein the means for selecting one of the access requests predicated on the comparison includes means for selecting the access request with the highest composite priority.

99. The crossbar switch of claim 96, further comprising means for programming the values of the assigned weight factors before they are assigned.

100. The crossbar switch of claim 96, further comprising means for increasing the composite request priority of each access request not selected or decreasing the composite request priority of the selected request.

101. The crossbar switch of claim 90, wherein the means for forwarding the selected access request to the respective memory device includes forwarding the selected access request to a memory interface.

102. A crossbar switch, comprising:

means for receiving from a respective device an access request to any one of a plurality of physical memory devices;

means for arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device.

103. The crossbar switch of claim 102, wherein:

the receiving means includes a plurality of input sorting units;

or the arbitration and selection means includes a plurality of merge and interleave units.

104. The crossbar switch of claim 103, wherein the receiving means further comprises a plurality of translation circuits and wherein each of the input sorting units receives the access requests through a respective one of the Translation circuits.

105. The crossbar switch of claim 104, wherein each of the translation circuits is capable of receiving an opcode and a virtual address from their respective device, translating the opcode to determine whether the access request is a read or a write, and mapping the virtual address into a physical address, and forwarding the translated opcode and mapped physical address to its respective input sorting unit.

106. The crossbar switch of claim 102, wherein receiving means furthermore buffers the access requests.

107. The crossbar switch of claim 106, wherein the receiving means includes a first-in, first-out queue for buffering the access requests.

108. The crossbar switch of claim 106, wherein each of the input sorting units is capable of stalling its respective device when its buffer is full.

109. The crossbar switch of claim 102, wherein the arbitration and selection means includes:

a priority generator for each input sorting unit capable of;

receiving a plurality of characteristics for the access request received by the input sorting unit;

receiving a plurality of operational characteristics; and

generating a composite request priority from the characteristics of the access requests and the operational characteristics;

a priority compare circuit capable of

comparing the composite request priorities generated by the priority generators; and

selecting one access request predicated on the comparison of the composite request priorities; and

a request multiplexer controlled by the priority compare circuit to output the selected access request.

110. The crossbar switch of claim 109, wherein the merge and interleave unit further includes:

a plurality of programmable registers;

a decode unit receiving the selected request from the request multiplexer to determine whether the selected request is a register operation and, if so, to send a plurality of control and data signals to the registers; and

an output multiplexer for combining register read data with request data for output.

111. The crossbar switch of claim 102, further comprising:

means for receiving and buffering read data from a respective one of the physical memory devices; and

means for receiving read data from the read buffers and forwarding the received read data to a respective one of the devices that generated the access request associated with the read data.

112. The crossbar switch of claim 111, wherein:

the receiving and buffering means includes a plurality of read buffers;

or the receiving and forwarding data includes a plurality of output management units.

113. The crossbar switch of claim 102, further comprising means for receiving the selected access request from the arbitration and selection means and forwarding the selected access request to a respective one of the physical memory devices.

114. The crossbar switch of claim 113, wherein the receiving and forwarding means comprises a plurality of memory interfaces.

115-154. -154. Cancelled.