Apparatus and methods for linking a processor and cache

• US 20040225830A1
• Filed: 05/06/2003
• Published: 11/11/2004
• Est. Priority Date: 05/06/2003
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: DeLano, Eric
• Application Number:
  US10/430,557
• Publication Number:
  US 20040225830A1
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 15/7846 On-chip cache and off-chip main memory

Abstract

A processing system includes a processor on a die, a cache memory external to the die, and a high-bandwidth interconnection between the processor and the cache memory. Where the cache is dynamic random access memory (DRAM), shorter latencies are generated than in traditional DRAM cache/processor configurations, yet higher density can be provided than available using SRAM caches.

Claims

1. A processing system comprising a processor on a die, a cache memory external to the die, and a high-bandwidth interconnection between the processor and the cache memory.

2. The processing system of claim 1 wherein the cache memory comprises dynamic random access memory.

3. The processing system of claim 1 wherein the high-bandwidth interconnection comprises a point-to-point differential signal connection.

4. The processing system of claim 3 wherein the high-bandwidth interconnection further comprises a plurality of differential signal pairs.

5. The processing system of claim 4 wherein the plurality comprises thirty-two differential signal pairs.

6. The processing system of claim 1 wherein the high-bandwidth interconnection comprises a plurality of unidirectional signal connections.

7. The processing system of claim 1 wherein the high-bandwidth interconnection comprises a transfer rate of up to about four giga-transfers per second.

8. The processing system of claim 1 wherein the high-bandwidth interconnection comprises a serializer/deserializer link.

9. A processing system comprising a processor, a cache memory comprising dynamic random access memory, and a link interconnection between the processor and the cache memory.

10. The processing system of claim 9 further comprising a die on which the processor is located, and wherein the cache memory is external to the die.

11. The processing system of claim 9 wherein the link interconnection comprises a point-to-point differential signal connection.

12. The processing system of claim 11 wherein the link interconnection further comprises sixteen differential signal pairs per direction.

13. A method for processing data located in a main memory using a processor configured to access the main memory, the method comprising:

providing a cache memory external to the processor;

writing data from the main memory to the cache memory; and

the processor accessing the cache memory using a high-bandwidth interconnection between the processor and the cache memory.

14. The method of claim 13 further comprising transferring data between the processor and the cache memory using a point-to-point differential signal.

15. The method of claim 13 wherein providing a cache memory comprises configuring the cache memory and the processor on different dies.

16. The method of claim 13 further comprising the processor accessing the data in the cache memory using dynamic random access.

17. The method of claim 13 wherein the processor accessing the cache memory is performed at up to about four giga-transfers per second.

18. A multi-chip module comprising a processor on a first chip, a cache memory on a second chip, and a link interconnection between the first and second chips.

19. The multi-chip module of claim 18 wherein the link interconnection connects the processor and the cache memory.

20. The multi-chip module of claim 18 wherein the second chip comprises dynamic random access memory.

21. The multi-chip module of claim 18 wherein the link interconnection comprises a plurality of unidirectional signal connections.

22. A cache memory adaptable for use with a processor on a die separate from the cache, comprising:

a dynamic random access memory; and

a high-bandwidth interconnection connected with the memory and configured for connection with the processor.

23. The cache memory of claim 22, wherein the high-bandwidth interconnection comprises a serializer/deserializer interconnection.

24. The cache memory of claim 22, wherein the high-bandwidth interconnection comprises a point-to-point interconnection.

25. The cache memory of claim 22, wherein high-bandwidth comprises up to about four giga-transfers per second.

26. A method of fabricating a processing system comprising:

providing a processor on a die;

providing a dynamic random access cache memory on another die; and

connecting the processor and the cache memory using a high-bandwidth interconnection.